A survey of high level synthesis languages, tools, and compilers for reconfigurable high performance computing L Daoud, D Zydek, H Selvaraj Advances in Systems Science: Proceedings of the International Conference on …, 2014 | 65 | 2014 |
Secure network-on-chip architectures for MPSoC: overview and challenges L Daoud 2018 IEEE 61st international midwest symposium on circuits and systems …, 2018 | 25 | 2018 |
High Level Synthesis Using Vivado HLS for Optimizations of SHA-3 HS Jacinto, L Daoud, N Rafla the 60th Midwest Symposium on Circuits and Systems (MWSCAS), 563 -- 566, 2017 | 25 | 2017 |
Analysis of Black Hole Router Attack in Network-on-Chip L Daoud, N Rafla 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019 | 24 | 2019 |
Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS) L Daoud, F Hussein, N Rafla 34th International Conference on Computers and Their Applications, 36-44, 2019 | 22 | 2019 |
Routing aware and runtime detection for infected network-on-chip routers L Daoud, N Rafla 2018 IEEE 61st International Midwest Symposium on Circuits and Systems …, 2018 | 21 | 2018 |
Faster processor allocation algorithms for mesh-connected cmps LB Daoud, MES Ragab, V Goulart 2011 14th Euromicro Conference on Digital System Design, 805-808, 2011 | 17 | 2011 |
Processor allocation algorithm based on frame combing with memorization for 2d mesh cmps LB Daoud, MES Ragab, V Goulart 2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2012 | 13 | 2012 |
Optimization of a Quantum-Secure Sponge-Based Hash Message Authentication Protocol M Latif, HS Jacito, L Daoud, N Rafla IEEE 61st International Midwest Symposium on Circuits and Systems, 984-987, 2018 | 10 | 2018 |
High performance bitwise or based submesh allocation for 2d mesh-connected cmps L Daoud, V Goulart 2013 Euromicro Conference on Digital System Design, 73-77, 2013 | 10 | 2013 |
Detection and prevention protocol for black hole attack in network-on-chip L Daoud, N Rafla Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip …, 2019 | 9 | 2019 |
A survey on design and implementation of floating point adder in FPGA L Daoud, D Zydek, H Selvaraj Progress in Systems Engineering: Proceedings of the Twenty-Third …, 2015 | 8 | 2015 |
A fully pipelined FPGA accelerator for scale invariant feature transform keypoint descriptor matching L Daoud, MK Latif, HS Jacinto, N Rafla Microprocessors and Microsystems 72, 102919, 2020 | 7 | 2020 |
High-Level Synthesis Optimization of AES-128/192/256 Encryption Algorithms L Daoud, F Hussein, N Rafla International Journal of Computers and Their Applications 29 (3), 129-136, 2019 | 6 | 2019 |
Real-time Bitstream Decompression Scheme for FPGAs Reconfiguration L Daoud, F Hussein, N Rafla 2018 IEEE 61st International Midwest Symposium on Circuits and Systems …, 2018 | 6 | 2018 |
Zynq-based SoC implementation of an induction machine control algorithm D Mohammadi, L Daoud, N Rafla, S Ahmed-Zaid 2016 IEEE 59th International Midwest Symposium on Circuits and Systems …, 2016 | 6 | 2016 |
A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA F Hussein, L Daoud, N Rafla Microprocessors and Microsystems 74, 103014, 2020 | 4 | 2020 |
Efficient mitigation technique for Black Hole router attack in Network-on-Chip L Daoud, N Rafla Microprocessors and Microsystems 94, 104658, 2022 | 3 | 2022 |
Runtime packet-dropping detection of faulty nodes in network-on-chip L Daoud, N Rafla 2019 32nd IEEE International System-on-Chip Conference (SOCC), 266-271, 2019 | 3 | 2019 |
Sift keypoint descriptor matching algorithm: A fully pipelined accelerator on fpga L Daoud, MK Latif, N Rafla Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018 | 3 | 2018 |