SAID: A supergate-aided logic synthesis flow for memristive crossbars V Tenace, RG Rizzo, D Bhattacharjee, A Chattopadhyay, A Calimera 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 372-377, 2019 | 18 | 2019 |
Performance profiling of embedded convnets under thermal-aware dvfs V Peluso, RG Rizzo, A Calimera Electronics 8 (12), 1423, 2019 | 14 | 2019 |
Inference on the edge: Performance analysis of an image classification task using off-the-shelf cpus and open-source convnets V Peluso, RG Rizzo, A Cipolletta, A Calimera 2019 Sixth International Conference on Social Networks Analysis, Management …, 2019 | 8 | 2019 |
Beyond ideal DVFS through ultra-fine grain vdd-hopping V Peluso, RG Rizzo, A Calimera, E Macii, M Alioto VLSI-SoC: System-on-Chip in the Nanoscale Era–Design, Verification and …, 2017 | 8 | 2017 |
Early bird sampling: a short-paths free error detection-correction strategy for data-driven VOS RG Rizzo, V Peluso, A Calimera, J Zhou, X Liu 2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017 | 7 | 2017 |
Approximate error detection-correction for efficient adaptive voltage over-scaling RG Rizzo, A Calimera, J Zhou Integration 63, 220-231, 2018 | 6 | 2018 |
Multiplication by inference using classification trees: A case-study analysis RG Rizzo, V Tenace, A Calimera 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 5 | 2018 |
Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection RG Rizzo, A Calimera Journal of Low Power Electronics and Applications 9 (2), 17, 2019 | 4 | 2019 |
Tunable Error Detection-Correction for Efficient Adaptive Voltage Over-Scaling RG Rizzo, A Calimera 2017 IEEE New Generation of CAS (NGCAS), 13-16, 2017 | 4 | 2017 |
AdapTTA: adaptive test-time augmentation for reliable embedded convnets L Mocerino, RG Rizzo, V Peluso, A Calimera, E Macii 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration …, 2021 | 3 | 2021 |
Tvfs: Topology voltage frequency scaling for reliable embedded convnets RG Rizzo, V Peluso, A Calimera IEEE Transactions on Circuits and Systems II: Express Briefs 68 (2), 672-676, 2020 | 3 | 2020 |
Efficacy of topology scaling for temperature and latency constrained embedded convnets V Peluso, RG Rizzo, A Calimera Journal of Low Power Electronics and Applications 10 (1), 10, 2020 | 3 | 2020 |
On the efficiency of early bird sampling (EBS) an error detection-correction scheme for data-driven voltage over-scaling RG Rizzo, V Peluso, A Calimera, J Zhou VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things: 25th …, 2019 | 3 | 2019 |
Design and characterization of analog-to-digital converters using graphene pn junctions RG Rizzo, S Miryala, A Calimera, E Macii, M Poncino Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 253-258, 2015 | 3 | 2015 |
Adaptive Test-Time Augmentation for Low-Power CPU L Mocerino, RG Rizzo, V Peluso, A Calimera, E Macii arXiv preprint arXiv:2105.06183, 2021 | 1 | 2021 |
Energy-Accuracy Scaling in Digital ICs: Static and Adaptive Design Methods and Tools RG Rizzo https://iris.polito.it/retrieve/handle/11583/2743228/274751 …, 2019 | 1* | 2019 |
On the Efficiency of AdapTTA: An Adaptive Test-Time Augmentation Strategy for Reliable Embedded ConvNets L Mocerino, RG Rizzo, V Peluso, A Calimera, E Macii IFIP/IEEE International Conference on Very Large Scale Integration-System on …, 2021 | | 2021 |
Energy-Efficient Speculative Computing for IoT ICs A Calimera, E Macii | | |