| Ultra-wide-band transmitter for low-power wireless body area networks: Design and evaluation J Ryckaert, C Desset, A Fort, M Badaroglu, V De Heyn, P Wambacq, ... IEEE transactions on circuits and systems I: Regular papers 52 (12), 2515-2525, 2005 | 295 | 2005 |
| A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18/spl mu/m CMOS J Ryckaert, M Badaroglu, V De Heyn, G Van der Plas, P Nuzzo, ... 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006 | 124 | 2006 |
| A 0.65-to-1.4 nJ/burst 3-to-10 GHz UWB all-digital TX in 90 nm CMOS for IEEE 802.15. 4a J Ryckaert, G Van der Plas, V De Heyn, C Desset, B Van Poucke, ... IEEE Journal of Solid-State Circuits 42 (12), 2860-2869, 2007 | 94 | 2007 |
| A CMOS ultra-wideband receiver for low data-rate communication J Ryckaert, M Verhelst, M Badaroglu, S D'Amico, V De Heyn, C Desset, ... IEEE Journal of Solid-State Circuits 42 (11), 2515-2527, 2007 | 87 | 2007 |
| Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition L Witters, H Arimura, F Sebaai, A Hikavyy, AP Milenin, R Loo, ... IEEE transactions on electron devices 64 (11), 4587-4593, 2017 | 79 | 2017 |
| A 0.65-to-1.4 nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15. 4a J Ryckaert, G Van der Plas, V De Heyn, C Desset, G Vanwijnsberghe, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 77 | 2007 |
| First demonstration of vertically stacked gate-all-around highly strained germanium nanowire pFETs E Capogreco, L Witters, H Arimura, F Sebaai, C Porret, A Hikavyy, R Loo, ... IEEE Transactions on Electron Devices 65 (11), 5145-5150, 2018 | 67 | 2018 |
| Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage V De Heyn, G Groeseneken, B Keppens, M Natarajan, L Vacaresse, ... 2001 IEEE International Reliability Physics Symposium Proceedings. 39th …, 2001 | 66 | 2001 |
| Influence of gate length on ESD-performance for deep sub micron CMOS technology K Bock, B Keppens, V De Heyn, G Groeseneken, LY Ching, A Naem Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 …, 1999 | 65 | 1999 |
| Characterization and modeling of transient device behavior under CDM ESD stress J Willemen, A Andreini, V De Heyn, K Esmark, M Etherton, H Gieser, ... Journal of electrostatics 62 (2-3), 133-153, 2004 | 63 | 2004 |
| The potential of FinFETs for analog and RF circuit applications P Wambacq, B Verbruggen, K Scheir, J Borremans, M Dehan, D Linten, ... IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2541-2551, 2007 | 59 | 2007 |
| Carrier-based UWB impulse radio: simplicity, flexibility, and pulser implementation in 0.18-micron CMOS J Ryckaert, M Badaroglu, C Desset, V De Heyn, G ven der Plas, ... 2005 IEEE International Conference on Ultra-Wideband, 432-437, 2005 | 53 | 2005 |
| First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers A Vandooren, J Franco, Z Wu, B Parvais, W Li, L Witters, A Walke, L Peng, ... 2018 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2018 | 38 | 2018 |
| 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525° C with improved reliability A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ... 2018 IEEE Symposium on VLSI Technology, 69-70, 2018 | 28 | 2018 |
| A fast start-up 3GHz–10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS V De Heyn, G Van der Plas, J Ryckaert, J Craninckx ESSCIRC 2007-33rd European Solid-State Circuits Conference, 484-487, 2007 | 26 | 2007 |
| Suitability of FinFET technology for low-power mixed-signal applications B Parvais, C Gustin, V De Heyn, J Loo, M Dehan, V Subramanian, ... 2006 IEEE International Conference on IC Design and Technology, 1-4, 2006 | 26 | 2006 |
| Contributions to standardization of transmission line pulse testing methodology B Keppens, V De Heyn, MN Iyer, G Groeseneken 2001 Electrical Overstress/Electrostatic Discharge Symposium, 456-462, 2001 | 26 | 2001 |
| 3-D sequential stacked planar devices featuring low-temperature replacement metal gate junctionless top devices with improved reliability A Vandooren, J Franco, B Parvais, Z Wu, L Witters, A Walke, W Li, L Peng, ... IEEE Transactions on Electron Devices 65 (11), 5165-5171, 2018 | 23 | 2018 |
| Performance and electrostatic improvement by high-pressure anneal on Si-passivated strained Ge pFinFET and gate all around devices with superior NBTI reliability H Arimura, L Witters, D Cott, H Dekkers, R Loo, J Mitard, LÅ Ragnarsson, ... 2017 Symposium on VLSI Technology, T196-T197, 2017 | 21 | 2017 |
| Test circuits for fast and reliable assessment of CDM robustness of I/O stages W Stadler, K Esmark, K Reynders, M Zubeidat, M Graf, W Wilkening, ... 2003 Electrical Overstress/Electrostatic Discharge Symposium, 1-9, 2003 | 20 | 2003 |
