| ATCache: Reducing DRAM cache latency via a small SRAM tag cache CC Huang, V Nagarajan Proceedings of the 23rd international conference on Parallel architectures …, 2014 | 131 | 2014 |
| Boomerang: A metadata-free architecture for control flow delivery R Kumar, CC Huang, B Grot, V Nagarajan 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 72 | 2017 |
| C3D: Mitigating the NUMA bottleneck via coherent DRAM caches CC Huang, R Kumar, M Elver, B Grot, V Nagarajan 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 30 | 2016 |
| Branch target buffer for a data processing apparatus R Kumar, B Grot, V Nagarajan, CC Huang | 27 | 2018 |
| Increasing cache capacity via critical-words-only cache CC Huang, V Nagarajan 2014 IEEE 32nd International Conference on Computer Design (ICCD), 125-132, 2014 | 12 | 2014 |
| DCA: a DRAM-cache-aware DRAM controller CC Huang, V Nagarajan, A Joshi SC'16: Proceedings of the International Conference for High Performance …, 2016 | 10 | 2016 |
| Optimizing cache utilization in modern cache hierarchies CC Huang The University of Edinburgh, 2016 | | 2016 |
