| OpenPiton: An Open Source Manycore Research Framework J Balkind, M McKeown, Y Fu, T Nguyen, Y Zhou, A Lavrov, M Shahrad, ... ASPLOS '16: Proceedings of the Twenty-First International Conference on …, 2016 | 284 | 2016 |
| Architectural implications of function-as-a-service computing M Shahrad, J Balkind, D Wentzlaff Proceedings of the 52nd annual IEEE/ACM international symposium on …, 2019 | 272 | 2019 |
| BYOC: A "Bring Your Own Core" Framework For Heterogeneous-ISA Research J Balkind, K Lim, M Schaffner, F Gao, G Chirkov, A Li, A Lavrov, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 66 | 2020 |
| Power and Energy Characterization of an Open Source 25-Core Manycore Processor. M McKeown, A Lavrov, M Shahrad, PJ Jackson, Y Fu, J Balkind, ... HPCA, 762-775, 2018 | 58 | 2018 |
| OpenPiton+ Ariane: The first open-source, SMP Linux-booting RISC-V system scaling from one to many cores J Balkind, K Lim, F Gao, J Tu, D Wentzlaff, M Schaffner, F Zaruba, L Benini Workshop on Computer Architecture Research with RISC-V (CARRV), 1-6, 2019 | 57 | 2019 |
| Piton: A manycore processor for multitenant clouds M McKeown, Y Fu, T Nguyen, Y Zhou, J Balkind, A Lavrov, M Shahrad, ... Ieee micro 37 (2), 70-80, 2017 | 39 | 2017 |
| Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs M Orenes-Vera, A Manocha, J Balkind, F Gao, JL Aragón, D Wentzlaff, ... Proceedings of the 49th Annual International Symposium on Computer …, 2022 | 29 | 2022 |
| Execution drafting: Energy efficiency through computation deduplication M Mckeown, J Balkind, D Wentzlaff 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 432-444, 2014 | 24 | 2014 |
| OpenPiton at 5: A nexus for open and agile hardware design J Balkind, TJ Chang, PJ Jackson, G Tziantzioulis, A Li, F Gao, A Lavrov, ... IEEE Micro 40 (4), 22-31, 2020 | 21 | 2020 |
| Project snowflake: Non-blocking safe manual memory management in. net M Parkinson, D Vytiniotis, K Vaswani, M Costa, P Deligiannis, ... Proceedings of the ACM on Programming Languages 1 (OOPSLA), 1-25, 2017 | 21 | 2017 |
| JuxtaPiton: Enabling Heterogeneous-ISA Research With RISC-V and SPARC FPGA Soft-cores K Lim, J Balkind, D Wentzlaff arXiv preprint arXiv:1811.08091, 2018 | 18 | 2018 |
| Cohort: Software-oriented acceleration for heterogeneous socs T Wei, N Turtayeva, M Orenes-Vera, O Lonkar, J Balkind Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 15 | 2023 |
| Wire sorts: A language abstraction for safe hardware composition M Christensen, T Sherwood, J Balkind, B Hardekopf Proceedings of the 42nd ACM SIGPLAN International Conference on Programming …, 2021 | 15 | 2021 |
| DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including … F Gao, TJ Chang, A Li, M Orenes-Vera, D Giri, PJ Jackson, A Ning, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 13 | 2023 |
| Fast behavioural rtl simulation of 10b transistor soc designs with metro-mpi G López-Paradís, B Li, A Armejach, S Wallentowitz, M Moretó, J Balkind 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 12 | 2023 |
| Loop rerolling for hardware decompilation ZD Sisco, J Balkind, T Sherwood, B Hardekopf Proceedings of the ACM on Programming Languages 7 (PLDI), 420-442, 2023 | 11 | 2023 |
| OpenPiton: an open source hardware platform for your research J Balkind, M McKeown, Y Fu, T Nguyen, Y Zhou, A Lavrov, M Shahrad, ... Communications of the ACM 62 (12), 79-87, 2019 | 9 | 2019 |
| Piton: A 25-core academic manycore research processor. M McKeown, Y Fu, TM Nguyen, Y Zhou, J Balkind, A Lavrov, M Shahrad, ... Hot Chips Symposium, 1-38, 2016 | 9* | 2016 |
| OpenPiton Optimizations Towards High Performance Manycores N Leyva, A Monemi, N Oliete-Escuín, G López-Paradís, X Abancens, ... Proceedings of the 16th International Workshop on Network on Chip …, 2023 | 5 | 2023 |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 4 | 2023 |
David WentzlaffAssociate Professor of Electrical Engineering, Princeton UniversityVerified email at princeton.edu
