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Jiajia Li
Jiajia Li
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Title
Cited by
Cited by
Year
ICCAD-2015 CAD contest in incremental timing-driven placement and benchmark suite
MC Kim, J Hu, J Li, N Viswanathan
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 921-926, 2015
902015
OpenROAD: Toward a self-driving, open-source digital layout implementation tool chain
T Ajayi, D Blaauw
Proceedings of Government Microcircuit Applications and Critical Technology …, 2019
782019
Mixed cell-height implementation for improved design quality in advanced nodes
S Dobre, AB Kahng, J Li
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 854-860, 2015
452015
A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction
K Han, J Li, AB Kahng, S Nath, J Lee
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
372015
Optimal generalized H-tree topology and buffering for high-performance and low-power clock distribution
K Han, AB Kahng, J Li
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
312018
Horizontal benchmark extension for improved assessment of physical CAD research
AB Kahng, H Lee, J Li
Proceedings of the 24th edition of the great lakes symposium on VLSI, 27-32, 2014
302014
Design implementation with noninteger multiple-height cells for improved design quality in advanced nodes
SA Dobre, AB Kahng, J Li
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
232017
Improved flop tray-based design implementation for power reduction
AB Kahng, J Li, L Wang
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016
222016
Optimizing stochastic circuits for accuracy-energy tradeoffs
A Alaghi, WTJ Chan, JP Hayes, AB Kahng, J Li
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 178-185, 2015
182015
PROBE: A placement, routing, back-end-of-line measurement utility
A Kahng, AB Kahng, H Lee, J Li
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
172017
Logic design partitioning for stacked power domains
K Blutman, H Fatemi, A Kapoor, AB Kahng, J Li, JP De Gyvez
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (11 …, 2017
172017
Trading accuracy for energy in stochastic circuit design
A Alaghi, WTJ Chan, JP Hayes, AB Kahng, J Li
ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (3), 1-30, 2017
152017
Enhancing sensitivity-based power reduction for an industry IC design context
H Fatemi, AB Kahng, H Lee, J Li, JP de Gyvez
Integration 66, 96-111, 2019
142019
Optimization of overdrive signoff
TB Chan, AB Kahng, J Li, S Nath
2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 344-349, 2013
142013
Floorplan and placement methodology for improved energy reduction in stacked power-domain design
K Blutman, H Fatemi, AB Kahng, A Kapoor, J Li, JP de Gyvez
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 444-449, 2017
132017
Revisiting 3DIC benefit with multiple tiers
WTJ Chan, AB Kahng, J Li
Proceedings of the 18th System Level Interconnect Prediction Workshop, 1-8, 2016
132016
A new methodology for reduced cost of resilience
AB Kahng, S Kang, J Li
Proceedings of the 24th edition of the great lakes symposium on VLSI, 157-162, 2014
122014
Nolo: A no-loop, predictive useful skew methodology for improved timing in ic implementation
TB Chan, AB Kahng, J Li
Fifteenth International Symposium on Quality Electronic Design, 504-509, 2014
122014
An improved methodology for resilient design implementation
AB Kahng, S Kang, J Li, J Pineda De Gyvez
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (4 …, 2015
102015
Reliability-constrained die stacking order in 3DICs under manufacturing variability
TB Chan, AB Kahng, J Li
International Symposium on Quality Electronic Design (ISQED), 16-23, 2013
62013
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