| Capability hardware enhanced RISC instructions: CHERI instruction-set architecture (version 7) RNM Watson, PG Neumann, J Woodruff, M Roe, H Almatary, J Anderson, ... University of Cambridge, Computer Laboratory, 2019 | 133 | 2019 |
| CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety H Xia, J Woodruff, S Ainsworth, NW Filardo, M Roe, A Richardson, ... Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019 | 84 | 2019 |
| Cornucopia: Temporal Safety for CHERI Heaps NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ... 2020 IEEE Symposium on Security and Privacy (SP). Los Alamitos, CA, USA …, 2020 | 81 | 2020 |
| Efficient tagged memory A Joannou, J Woodruff, R Kovacsics, SW Moore, A Bradbury, H Xia, ... 2017 IEEE International Conference on Computer Design (ICCD), 641-648, 2017 | 79 | 2017 |
| CHERI Concentrate: Practical Compressed Capabilities J Woodruff, A Joannou, H Xia, B Davis, PG Neumann, RNM Watson, ... IEEE Transactions on Computers, 2019 | 76 | 2019 |
| CheriRTOS: A Capability Model for Embedded Devices H Xia, J Woodruff, H Barral, L Esswood, A Joannou, R Kovacsics, ... 2018 IEEE 36th International Conference on Computer Design (ICCD), 92-99, 2018 | 31 | 2018 |
| A Secret-Free Hypervisor: Rethinking Isolation in the Age of Speculative Vulnerabilities H Xia, D Zhang, W Liu, I Haller, B Sherwin, D Chisnall 2022 IEEE Symposium on Security and Privacy (SP), 1544-1544, 2022 | 14 | 2022 |
| Capability memory protection for embedded systems H Xia University of Cambridge, Computer Laboratory, 2021 | 7 | 2021 |
