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Vasilis Thanasoulis
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Neuromorphic hardware in the loop: Training a deep spiking network on the brainscales wafer-scale system
S Schmitt, J Klähn, G Bellec, A Grübl, M Guettler, A Hartel, S Hartmann, ...
2017 international joint conference on neural networks (IJCNN), 2227-2234, 2017
1192017
Pattern representation and recognition with accelerated analog neuromorphic systems
MA Petrovici, S Schmitt, J Klähn, D Stöckel, A Schroeder, G Bellec, J Bill, ...
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
182017
Dedicated fpga communication architecture and design for a large-scale neuromorphic system
V Thanasoulis, J Partzsch, S Hartmann, C Mayr, R Schüffny
2012 19th IEEE International Conference on Electronics, Circuits, and …, 2012
112012
Classification With deep neural networks on an accelerated analog neuromorphic system
S Schmitt, J Klähn, G Bellec, A Grübl, M Güttler, A Hartel, S Hartmann, ...
Proceedings of the 2017 IEEE International Joint Conference on Neural Networks, 2017
92017
Server side hashing core exceeding 3 Gbps of throughput
HE Michail, GA Panagiotakopoulos, VN Thanasoulis, AP Kakarountas, ...
International Journal of Security and Networks 2 (3-4), 228-238, 2007
92007
Efficient Pipelined Hardware Implementation of RIPEMD-160 Hash Function
HE Michail, VN Thanasoulis, GA Panagiotakopoulos, AP Kakarountas, ...
International Journal of Electronics, Circuits and Systems 2 (2), 2008
62008
A pulse communication flow ready for accelerated neuromorphic experiments
V Thanasoulis, B Vogginger, J Partzsch, R Schüffny
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 265-268, 2014
42014
Temporal and system level modifications for high speed VLSI implementations of cryptographic core
HE Michail, AP Kakarountas, AS Milidonis, GA Panagiotakopoulos, ...
2006 13th IEEE International Conference on Electronics, Circuits and Systems …, 2006
42006
Configurable pulse routing architecture for accelerated multi-node neuromorphic systems
V Thanasoulis, J Partzsch, B Vogginger, R Schüffny
2014 21st IEEE International Conference on Electronics, Circuits and Systems …, 2014
22014
Long-term pulse stimulation and recording in an accelerated neuromorphic system
V Thanasoulis, J Partzsch, B Vogginger, C Mayr, R Schüffny
2012 19th IEEE International Conference on Electronics, Circuits, and …, 2012
22012
Analysis and Development of a Communication Infrastructure for a Wafer-Scale Neuromorphic System
V Thanasoulis
TUDpress, 2019
12019
Application Of Novel Techniques In RIPEMD-160 Hash Function Aiming At High-Throughput
H Michail, V Thanasoulis, D Schinianakis, G Panagiotakopoulos, C Goutis
HIGH PERFORMANCE COMPUTING & SIMULATION (HPCS 2008), 344, 2008
12008
Server side hashing core exceeding 3 Gbps of throughput
AP Kakarountas, VN Thanasoulis, HE Michail, GA Panagiotakopoulos, ...
Inderscience Enterprises Ltd, 2007
2007
Temporal and system level modifications for high speed VLSI implementations of cryptographic core
VN Thanasoulis, AS Milidonis, AP Kakarountas, CE Goutis, ...
2006
Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core
AS Milidonis, AP Kakarountas, HE Michail, GA Panagiotakopoulos, ...
2006
Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA
V Thanasoulis, B Vogginger, J Partzsch, C Mayr
2021 28th IEEE International Conference on Electronics, Circuits, and …, 0
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