| A biological-realtime neuromorphic system in 28 nm CMOS using low-leakage switched capacitor circuits C Mayr, J Partzsch, M Noack, S Hänzsche, S Scholze, S Höppner, ... IEEE transactions on biomedical circuits and systems 10 (1), 243-254, 2015 | 82 | 2015 |
| A 32 GBit/s communication SoC for a waferscale neuromorphic system S Scholze, H Eisenreich, S Höppner, G Ellguth, S Henker, M Ander, ... Integration 45 (1), 61-75, 2012 | 51 | 2012 |
| 10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS B Noethen, O Arnold, EP Adeva, T Seifert, E Fischer, S Kunze, E Matúš, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 50 | 2014 |
| A fast-locking ADPLL with instantaneous restart capability in 28-nm CMOS technology S Höppner, S Haenzsche, G Ellguth, D Walter, H Eisenreich, R Schüffny IEEE Transactions on Circuits and Systems II: Express Briefs 60 (11), 741-745, 2013 | 47 | 2013 |
| Memory-efficient deep learning on a SpiNNaker 2 prototype C Liu, G Bellec, B Vogginger, D Kappel, J Partzsch, F Neumärker, ... Frontiers in neuroscience, 840, 2018 | 45 | 2018 |
| A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS D Walter, S Höppner, H Eisenreich, G Ellguth, S Henker, S Hänzsche, ... 2012 IEEE International Solid-State Circuits Conference, 180-182, 2012 | 45 | 2012 |
| Spinnaker 2: A 10 million core processor system for brain simulation and machine learning C Mayr, S Hoeppner, S Furber arXiv preprint arXiv:1911.02385, 2019 | 43 | 2019 |
| VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality S Scholze, S Schiefer, J Partzsch, S Hartmann, CG Mayr, S Höppner, ... Frontiers in neuroscience 5, 117, 2011 | 43 | 2011 |
| Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS M Noack, J Partzsch, CG Mayr, S Hänzsche, S Scholze, S Höppner, ... Frontiers in neuroscience 9, 10, 2015 | 38 | 2015 |
| A compact clock generator for heterogeneous GALS MPSoCs in 65-nm CMOS technology S Hoppner, H Eisenreich, S Henker, D Walter, G Ellguth, R Schuffny IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (3), 566-570, 2012 | 36 | 2012 |
| A heterogeneous SDR MPSoC in 28 nm CMOS for low-latency wireless applications S Haas, T Seifert, B Nöthen, S Scholze, S Höppner, A Dixius, EP Adeva, ... Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 33 | 2017 |
| A power management architecture for fast per-core DVFS in heterogeneous MPSoCs S Höppner, C Shao, H Eisenreich, G Ellguth, M Ander, R Schüffny 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 261-264, 2012 | 31 | 2012 |
| A fixed point exponential function accelerator for a neuromorphic many-core system J Partzsch, S Höppner, M Eberlein, R Schüffny, C Mayr, DR Lester, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 30 | 2017 |
| A 335Mb/s 3.9mm265nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates M Winter, S Kunze, EP Adeva, B Mennenga, E Matûs, G Fettweis, ... 2012 IEEE International Solid-State Circuits Conference, 216-218, 2012 | 29 | 2012 |
| Efficient reward-based structural plasticity on a SpiNNaker 2 prototype Y Yan, D Kappel, F Neumärker, J Partzsch, B Vogginger, S Höppner, ... IEEE transactions on biomedical circuits and systems 13 (3), 579-591, 2019 | 25 | 2019 |
| A 12bit 4MS/s SAR ADC with Configurable Redundancy in 28nm CMOS Technology RS S Haenzsche, S Hoppner, G Ellguth Circuits and Systems II: Express Briefs, IEEE Transactions on 61 (11), 835,839, 2014 | 25* | 2014 |
| Reducing the computational footprint for real-time BCPNN learning B Vogginger, R Schüffny, A Lansner, L Cederström, J Partzsch, ... Frontiers in neuroscience 9, 2, 2015 | 23 | 2015 |
| Dynamic voltage and frequency scaling for neuromorphic many-core systems S Höppner, Y Yan, B Vogginger, A Dixius, J Partzsch, F Neumärker, ... 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 22 | 2017 |
| An energy efficient multi-Gbit/s NoC transceiver architecture with combined AC/DC drivers and stoppable clocking in 65 nm and 28 nm CMOS S Höppner, D Walter, T Hocker, S Henker, S Hänzsche, D Sausner, ... IEEE Journal of Solid-State Circuits 50 (3), 749-762, 2015 | 21 | 2015 |
| Spinnaker2-towards extremely efficient digital neuromorphics and multi-scale brain emulation S Höppner, C Mayr Proc. NICE, 2018 | 18 | 2018 |
Christian MayrProfessor, Technische Universität DresdenVerified email at tu-dresden.de
