| Highly scaled ruthenium interconnects S Dutta, S Kundu, A Gupta, G Jamieson, JFG Granados, J Bömmels, ... IEEE Electron Device Letters 38 (7), 949-951, 2017 | 94 | 2017 |
| Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ... 2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019 | 84 | 2019 |
| Sub-100 nm2 Cobalt Interconnects S Dutta, S Beyne, A Gupta, S Kundu, S Van Elshocht, H Bender, ... IEEE Electron Device Letters 39 (5), 731-734, 2018 | 74 | 2018 |
| High-aspect-ratio ruthenium lines for buried power rail A Gupta, S Kundu, L Teugels, J Bommels, C Adelmann, N Heylen, ... 2018 IEEE International Interconnect Technology Conference (IITC), 4-6, 2018 | 63 | 2018 |
| Device-, circuit-& block-level evaluation of CFET in a 4 track library P Schuddinck, O Zografos, P Weckx, P Matagne, S Sarkar, Y Sherazi, ... 2019 Symposium on VLSI Technology, T204-T205, 2019 | 58 | 2019 |
| Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery J Ryckaert, A Gupta, A Jourdain, B Chava, G Van der Plas, D Verkest, ... 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 50-52, 2019 | 58 | 2019 |
| RC Benefits of Advanced Metallization Options I Ciofi, PJ Roussel, R Baert, A Contino, A Gupta, K Croes, CJ Wilson, ... IEEE transactions on electron devices 66 (5), 2339-2345, 2019 | 57 | 2019 |
| Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ... IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020 | 41 | 2020 |
| SRAM with buried power distribution to improve write margin and performance in advanced technology nodes SM Salahuddin, KA Shaik, A Gupta, B Chava, M Gupta, P Weckx, ... IEEE electron device letters 40 (8), 1261-1264, 2019 | 36 | 2019 |
| PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch P Schuddinck, FM Bufler, Y Xiang, A Farokhnejad, G Mirabelli, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 34 | 2022 |
| Magnonic Band Structure in Vertical Meander-Shaped Thin Films G Gubbiotti, A Sadovnikov, E Beginin, S Nikitov, D Wan, A Gupta, ... Physical Review Applied 15 (1), 014061, 2021 | 31 | 2021 |
| Alternative metals: from ab initio screening to calibrated narrow line models C Adelmann, K Sankaran, S Dutta, A Gupta, S Kundu, G Jamieson, ... 2018 IEEE International Interconnect Technology Conference (IITC), 154-156, 2018 | 29 | 2018 |
| Inflection points in interconnect research and trends for 2nm and beyond in order to solve the RC bottleneck Z Tőkei, V Vega, G Murdoch, M O’Toole, K Croes, R Baert, ... 2020 IEEE International Electron Devices Meeting (IEDM), 32.2. 1-32.2. 4, 2020 | 28 | 2020 |
| Buried power SRAM DTCO and system-level benchmarking in N3 S Salahuddin, M Perumkunnil, ED Litta, A Gupta, P Weckx, J Ryckaert, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 26 | 2020 |
| Characterization of sintered inkjet‐printed silicon nanoparticle thin films for thermoelectric devices E Drahi, A Gupta, S Blayac, S Saunier, P Benaben physica status solidi (a) 211 (6), 1301-1307, 2014 | 23 | 2014 |
| Scaled FinFETs connected by using both wafer sides for routing via buried power rails A Veloso, A Jourdain, D Radisic, R Chen, G Arutchelvan, B O’Sullivan, ... IEEE Transactions on Electron Devices 69 (12), 7173-7179, 2022 | 21 | 2022 |
| Buried power rail metal exploration towards the 1 nm node A Gupta, D Radisic, JW Maes, OV Pedreira, JP Soulié, N Jourdan, ... 2021 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2021 | 21 | 2021 |
| Ruthenium interconnects with 58 nm2 cross-section area using a metal-spacer process S Dutta, S Kundu, L Wen, G Jamieson, K Croes, A Gupta, J Bömmels, ... 2017 ieee international interconnect technology conference (iitc), 1-3, 2017 | 20 | 2017 |
| Buried power rail integration with Si FinFETs for CMOS scaling beyond the 5 nm node A Gupta, H Mertens, Z Tao, S Demuynck, J Bömmels, G Arutchelvan, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 19 | 2020 |
| Metal reliability mechanisms in Ruthenium interconnects OV Pedreira, M Stucchi, A Gupta, VV Gonzalez, M van der Veen, ... 2020 IEEE International Reliability Physics Symposium (IRPS), 1-7, 2020 | 17 | 2020 |
