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Ricardo Augusto da Luz Reis
Ricardo Augusto da Luz Reis
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Title
Cited by
Cited by
Year
Fault-tolerance techniques for SRAM-based FPGAs
FL Kastensmidt, L Carro, RA da Luz Reis
Springer, 2006
3432006
Designing fault tolerant systems into SRAM-based FPGAs
F Lima, L Carro, R Reis
Proceedings of the 40th annual Design Automation Conference, 650-655, 2003
2042003
Radiation effects on embedded systems
R Velazco, P Fouillat, R Reis
Springer Science & Business Media, 2007
1982007
A fault injection analysis of Virtex FPGA TMR design methodology
F Lima, C Carmichael, J Fabula, R Padovani, R Reis
RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on …, 2001
1752001
Designing fault-tolerant techniques for SRAM-based FPGAs
FG de Lima Kastensmidt, G Neuberger, RF Hentschke, L Carro, R Reis
IEEE Design & Test of Computers 21 (6), 552-562, 2004
1742004
Analyzing area and performance penalty of protecting different digital modules with Hamming code and triple modular redundancy
R Hentschke, F Marques, F Lima, L Carro, A Susin, R Reis
Proceedings. 15th Symposium on Integrated Circuits and Systems Design, 95-100, 2002
1562002
A multiple bit upset tolerant SRAM memory
G Neuberger, F De Lima, L Carro, R Reis
ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003
942003
Design of regular layouts to improve predictability
C Menezes, C Meinhardt, R Reis, R Tavares
2006 International Caribbean Conference on Devices, Circuits and Systems, 67-72, 2006
912006
An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories
G Neuberger, FG de Lima Kastensmidt, R Reis
IEEE Design & Test of Computers 22 (1), 50-58, 2005
752005
Predictive Evaluation of Electrical Characteristics of Sub-22nm Finfet Technologies Under Device Geometry Variations
R MEINHARDT, C., ZIMPECK, A., REIS
Microelectronics Reliability 54, 2014
642014
An Effective Method for Simultaneous Gate Sizing and Vth Assignment using Lagrangian Relaxation
Flach, Reimann, Posser, Johann, Reis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
602014
An Effective Method for Simultaneous Gate Sizing and Vth Assignment using Lagrangian Relaxation
R FLACH, G., REIMANN, T., POSSER, G., JOHANN, G., REIS
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, 2014
602014
Designing and testing fault-tolerant techniques for sram-based fpgas
FL Kastensmidt, G Neuberger, L Carro, R Reis
Proceedings of the 1st conference on Computing frontiers, 419-432, 2004
602004
Circuit Design for Reliability
G REIS, R., CAO, Y., WIRTH
Springer, 2015
592015
Circuit Design for Reliability
G REIS, R., CAO, Y., WIRTH
Springer, 2015
592015
A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability
F Rosa, F Kastensmidt, R Reis, L Ost
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2015
552015
On the evolution of remote laboratories for prototyping digital electronic systems
LS Indrusiak, M Glesner, R Reis
IEEE Transactions on Industrial Electronics 54 (6), 3069-3077, 2007
512007
A low-cost solution for deploying processor cores in harsh environments
M Violante, C Meinhardt, R Reis, MS Reorda
IEEE Transactions on Industrial Electronics 58 (7), 2617-2626, 2011
482011
Using machine learning techniques to evaluate multicore soft error reliability
FR da Rosa, R Garibotti, L Ost, R Reis
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (6), 2151-2164, 2019
462019
Revisiting automated physical synthesis of high-performance clock networks
MR Guthaus, G Wilke, R Reis
ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (2 …, 2013
462013
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