Peter Beerel

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Souvik KunduResearch Scientist, Intel Labs; Ph.D - University of Southern CaliforniaVerified email at intel.com
Gourav DattaAmazon Inc., University of Southern CaliforniaVerified email at usc.edu
Massoud PedramCharles Lee Powell Professor of Electrical Engineering & Computer Science, Univ of SouthernVerified email at usc.edu
Keith ChuggProfessor of Electrical Engineering, USCVerified email at usc.edu
Ken StevensProfessor of electrical and computer engineering, university of utahVerified email at ece.utah.edu
Chris MyersUniversity of UtahVerified email at ece.utah.edu
Ney Laert Vilar CalazansInvited Researcher at the Graduate Program on Microelectronics (PGMICRO), UFRGSVerified email at inf.ufrgs.br
Ramy N. TadrosQualcommVerified email at qti.qualcomm.com
Matheus Trevisan MoreiraMetaVerified email at meta.com
Akhilesh JaiswalAssistant Professor, University of Wisconsin-MadisonVerified email at wisc.edu
Ran GinosarProfessor of EE & CS, TechnionVerified email at ee.technion.ac.il
Sourya DeyGaloisVerified email at galois.com
Arash SaifhashemiResearch Scientist, Intel LabsVerified email at intel.com
Huimei ChengUniversity of Southern CaliforniaVerified email at usc.edu
Mike DaviesDirector, Neuromorphic Computing Lab, IntelVerified email at intel.com
Pierluigi NuzzoEECS Department, University of California, BerkeleyVerified email at eecs.berkeley.edu
Jerry R. BurchSynopsys, Inc.Verified email at fun-journey.com
Steven NowickProfessor Emeritus of Computer Science, Columbia UniversityVerified email at cs.columbia.edu
Mehrdad Najibi,Senior Member of Technical Staff, Cadence Design SystemsVerified email at usc.edu
Mahdi NazemiUniversity of Southern CaliforniaVerified email at usc.edu

Peter Beerel

Professor of Electrical and Computer Engineering, USC

Verified email at usc.edu - Homepage

Machine Learning Hardware Security Superconducting Electronics CAD/VLSI


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Optimization of cell subtypes in a hierarchical design flow F Eaton, P Beerel US Patent 6,854,096, 2005	284	2005
A designer's guide to asynchronous VLSI PA Beerel, RO Ozdag, M Ferretti Cambridge University Press, 2010	279	2010
Automatic gate-level synthesis of speed-independent circuits Beerel, Meng 1992 IEEE/ACM International Conference on Computer-Aided Design, 581-586, 1992	188	1992
Speculative completion for the design of high-performance asynchronous dynamic adders SM Nowick, KY Yun, PA Beerel, AE Dooply Proceedings Third International Symposium on Advanced Research in …, 1997	162	1997
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver KY Yun, PA Beerel, V Vakilotojar, AE Dooply, J Arceo IEEE transactions on very large scale integration (VLSI) systems 6 (4), 643-655, 1998	154	1998
High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells M Ferretti, RO Ozdag, PA Beerel 10th International Symposium on Asynchronous Circuits and Systems, 2004 …, 2004	146	2004
High-performance asynchronous pipeline circuits KY Yun, PA Beerel, J Arceo Proceedings Second International Symposium on Advanced Research in …, 1996	131	1996
Slack matching asynchronous designs PA Beerel, A Lines, M Davies, NH Kim 12th IEEE International Symposium on Asynchronous Circuits and Systems …, 2006	122	2006
Spike-thrift: Towards energy-efficient deep spiking neural networks by limiting spiking activity via attention-guided compression S Kundu, G Datta, M Pedram, PA Beerel Proceedings of the IEEE/CVF winter conference on applications of computer …, 2021	119	2021
Proteus: An ASIC flow for GHz asynchronous designs PA Beerel, GD Dimou, AM Lines IEEE Design & Test of Computers 28 (5), 36-51, 2011	116	2011
RAPPID: An asynchronous instruction length decoder S Rotem, K Stevens, R Ginosar, P Beerel, C Myers, K Yun, R Kol, C Dike, ... Proceedings. Fifth International Symposium on Advanced Research in …, 1999	116	1999
An asynchronous instruction length decoder KS Stevens, S Rotem, R Ginosar, P Beerel, CJ Myers, KY Yun, R Koi, ... IEEE Journal of solid-state circuits 36 (2), 217-228, 2001	115	2001
High-speed QDI asynchronous pipelines RO Ozdag, PA Beerel Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002	106	2002
Single-track asynchronous pipeline templates using 1-of-N encoding M Ferretti, PA Beerel Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002	99	2002
Safe BDD minimization using don't cares Y Hong, PA Beerel, JR Burch, KL McMillan Proceedings of the 34th annual Design Automation Conference, 208-213, 1997	91	1997
Semi-modularity and testability of speed-independent circuits PA Beerel, THY Meng Integration 13 (3), 301-322, 1992	85	1992
Blade--a timing violation resilient asynchronous template D Hand, MT Moreira, HH Huang, D Chen, F Butzke, Z Li, M Gibiluka, ... 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015	75	2015
Symbolic techniques for performance analysis of timed systems based on average time separation of events A Xie, PA Beerel Proceedings Third International Symposium on Advanced Research in …, 1997	75	1997
Bounding average time separations of events in stochastic timed Petri nets with choice A Xie, S Kim, PA Beerel Proceedings. Fifth International Symposium on Advanced Research in …, 1999	74	1999
ColdFlux superconducting EDA and TCAD tools project: Overview and progress CJ Fourie, K Jackman, MM Botha, S Razmkhah, P Febvre, CL Ayala, Q Xu, ... IEEE Transactions on Applied Superconductivity 29 (5), 1-7, 2019	69	2019

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