Constantinos Efstathiou

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	All	Since 2019
Citations	1881	340
h-index	20	10
i10-index	35	10

160

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Co-authors

Haridimos T. VergosProfessor, Computer Engineering & Informatics Dept, University of PatrasVerified email at ceid.upatras.gr
Dimitris NikolosProfessor, Computer Engineering & Informatics Dept, University of PatrasVerified email at ceid.upatras.gr
Ioannis VoyiatzisUniversity of West AtticaVerified email at uniwa.gr
Kiamal PekmestziEmeritus Professor, Electrical & Computer Eng., National Technical Univ. of AthensVerified email at cs.ntua.gr
Yiorgos TsiatouhasUniversity of IoanninaVerified email at cse.uoi.gr
Giorgos DimitrakopoulosProfessor, ECE, Democritus University of ThraceVerified email at ee.duth.gr
Hera AntonopoulouProfessor at the Dept. of Management Science and Technology, University of PatrasVerified email at upatras.gr
John KalamatianosFellow Design Engineer, AMD ResearchVerified email at amd.com
Athanasios MilidonisUniversity of West AtticaVerified email at uniwa.gr
Zaher OwdaUniversity of SiegenVerified email at uni-siegen.de
Paris KitsosProfessor of Electrical & Computer Engineering Department, University of the PeloponneseVerified email at uop.gr
Ioannis KouretasUniversity of PatrasVerified email at upatras.gr
Athanasios KakarountasUniversity of ThessalyVerified email at uth.gr
Kostas TsoumanisNational Technical University of Athens

Constantinos Efstathiou

Professor, Dept. of Informatics and Computer Engineering, University of West Attica

Verified email at uniwa.gr - Homepage

Computer Arithmetic Computer Architecture VLSI Design and Testing Nanoelectronics


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High-speed parallel-prefix module 2/sup n/-1 adders L Kalampoukas, D Nikolos, C Efstathiou, HT Vergos, J Kalamatianos IEEE Transactions on Computers 49 (7), 673-680, 2000	204	2000
Diminished-one modulo 2/sup n/+ 1 adder design HT Vergos, C Efstathiou, D Nikolos IEEE Transactions on Computers 51 (12), 1389-1399, 2002	201	2002
Fast parallel-prefix modulo 2/sup n/+ 1 adders C Efstathiou, HT Vergos, D Nikolos IEEE Transactions on Computers 53 (9), 1211-1216, 2004	129	2004
Efficient diminished-1 modulo 2/sup n/+ 1 multipliers C Efstathiou, HT Vergos, G Dimitrakopoulos, D Nikolos IEEE Transactions on Computers 54 (4), 491-496, 2005	97	2005
Modified Booth modulo 2/sup n/-1 multipliers C Efstathiou, HT Vergos, D Nikolos IEEE Transactions on Computers 53 (3), 370-374, 2004	93	2004
Area-time efficient modulo 2/sup n/-1 adder design C Efstathiou, D Nikolos, J Kalamatianos IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1994	92	1994
Design of efficient modulo 2n+ 1 multipliers HT Vergos, C Efstathiou IET Computers & Digital Techniques 1 (1), 49-57, 2007	84	2007
Modulo 2/sup n//spl plusmn/1 adder design using select-prefix blocks C Efstathiou, HT Vergos, D Nikolos IEEE Transactions on Computers 52 (11), 1399-1406, 2003	83	2003
An optimized modified booth recoder for efficient design of the add-multiply operator K Tsoumanis, S Xydis, C Efstathiou, N Moschopoulos, K Pekmestzi IEEE Transactions on Circuits and Systems I: Regular Papers 61 (4), 1133-1143, 2014	73	2014
A Unifying Approach for Weighted and Diminished-1 Modulo Addition HT Vergos, C Efstathiou IEEE Transactions on Circuits and Systems II: Express Briefs 55 (10), 1041-1045, 2008	67	2008
New high-speed multioutput carry look-ahead adders C Efstathiou, Z Owda, Y Tsiatouhas IEEE Transactions on Circuits and Systems II: Express Briefs 60 (10), 667-671, 2013	55	2013
New architectures for modulo 2n-1 adders G Dimitrakopoulos, DG Nikolos, HT Vergos, D Nikolos, C Efstathiou 2005 12th IEEE International Conference on Electronics, Circuits and Systems …, 2005	48	2005
Efficient modulo 2n+ 1 adder architectures HT Vergos, C Efstathiou Integration 42 (2), 149-157, 2009	38	2009
Handling zero in diminished-one modulo 2ⁿ + 1 adders C Efstathiou, HT Vergos, D Nikolos International Journal of Electronics 90 (2), 133-144, 2003	35	2003
A concurrent BIST architecture based on monitoring square windows I Voyiatzis, T Haniotakis, C Efstathiou, H Antonopoulou 5th International Conference on Design & Technology of Integrated Systems in …, 2010	31	2010
An efficient TSC 1-out-of-3 code checker AM Paschalis, C Efstathiou, C Halatsis IEEE transactions on computers 39 (3), 407-411, 1990	29	1990
Input vector monitoring concurrent BIST architecture using SRAM cells I Voyiatzis, C Efstathiou IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (7 …, 2013	28	2013
Diminished-1 modulo 2n+ 1 squarer design HT Vergos, C Efstathiou IEE Proceedings-Computers and Digital Techniques 152 (5), 561-566, 2005	21	2005
On the design of efficient modular adders HT Vergos, C EFSTATHIOU Journal of Circuits, Systems, and Computers 14 (05), 965-972, 2005	20	2005
A family of parallel-prefix modulo 2/sup n/-1 adders G Dimitrakopoulos, HT Vergos, D Nikolos, C Efstathiou Proceedings IEEE International Conference on Application-Specific Systems …, 2003	20	2003

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