| Redundancy-reduced MobileNet acceleration on reconfigurable logic for ImageNet classification J Su, J Faraone, J Liu, Y Zhao, DB Thomas, PHW Leong, PYK Cheung International Symposium on Applied Reconfigurable Computing, 16-28, 2018 | 42 | 2018 |
| Loop splitting for efficient pipelining in high-level synthesis J Liu, J Wickerson, GA Constantinides 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom …, 2016 | 38 | 2016 |
| Offline synthesis of online dependence testing: Parametric loop pipelining for HLS J Liu, S Bayliss, GA Constantinides 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 34 | 2015 |
| Parallel implementations of the fast gradient method for high-speed MPC H Peyrl, A Zanarini, T Besselmann, J Liu, MA Boéchat Control Engineering Practice 33, 22-34, 2014 | 33 | 2014 |
| Polyhedral-based Dynamic Loop Pipelining for High-Level Synthesis J Liu, J Wickerson, S Bayliss, GA Constantinides IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 23 | 2017 |
| Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs Y Zhao, X Gao, X Guo, J Liu, E Wang, R Mullins, PYK Cheung, ... 2019 International Conference on Field-Programmable Technology (ICFPT), 45-53, 2019 | 22 | 2019 |
| FPGA implementation of an interior point method for high-speed model predictive control J Liu, H Peyrl, A Burg, GA Constantinides 2014 24th International Conference on Field Programmable Logic and …, 2014 | 17 | 2014 |
| An FPGA implementation of the fast gradient method for solving the model predictive pulse pattern control problem H Peyrl, J Liu, T Geyer 2013 IEEE International Symposium on Sensorless Control for Electrical …, 2013 | 12 | 2013 |
| An architecture for solving quadratic programs with the fast gradient method on a field programmable gate array MA Boéchat, J Liu, H Peyrl, A Zanarini, T Besselmann 21st Mediterranean Conference on Control and Automation, 1557-1562, 2013 | 11 | 2013 |
| Tile Size Selection for Optimized Memory Reuse in High-Level Synthesis J Liu, J Wickerson, GA Constantinides Field Programmable Logic and Applications (FPL), 2017 27th International …, 2017 | 7 | 2017 |
| Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies J Liu, J Wickerson, S Bayliss, GA Constantinides Signals, Systems, and Computers, 2017 51st Asilomar Conference on, 126-130, 2017 | 3 | 2017 |
| Parametric polyhedral optimisation for high-level synthesis J Liu Imperial College London, 2017 | | 2017 |
George ConstantinidesImperial College LondonVerified email at ic.ac.uk
