Tůrur BiskopstÝ StrÝm
Tůrur BiskopstÝ StrÝm
Compute, Denmarks Technical University
Verified email at dtu.dk
TitleCited byYear
A desktop 3d printer in safety-critical Java
TB StrÝm, M Schoeberl
Proceedings of the 10th International Workshop on Java Technologies for Real†…, 2012
132012
Chip-multiprocessor hardware locks for safety-critical Java
TB StrÝm, W Puffitsch, M Schoeberl
Proceedings of the 11th International Workshop on Java Technologies for Real†…, 2013
72013
Certifiable Java for embedded systems
M Schoeberl, AE Dalsgaard, RR Hansen, SE Korsholm, AP Ravn, ...
Proceedings of the 12th International Workshop on Java Technologies for Real†…, 2014
62014
Hardware locks for a real‐time Java chip multiprocessor
TB StrÝm, W Puffitsch, M Schoeberl
Concurrency and Computation: Practice and Experience 29 (6), e3950, 2017
52017
Safety‐critical Java for embedded systems
M Schoeberl, AE Dalsgaard, RR Hansen, SE Korsholm, AP Ravn, ...
Concurrency and Computation: Practice and Experience 29 (22), e3963, 2017
32017
Hardlock: A Concurrent Real-Time Multicore Locking Unit
TB StrÝm, M Schoeberl
2018 IEEE 21st International Symposium on Real-Time Distributed Computing†…, 2018
22018
Scratchpad Memories with Ownership
M Schoeberl, TB StrÝm, O Baris, J SparsÝ
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE†…, 2019
12019
Multiprocessor Priority Ceiling Emulation for Safety-Critical Java
TB StrÝm, M Schoeberl
Proceedings of the 13th International Workshop on Java Technologies for Real†…, 2015
12015
Hardware locks with priority ceiling emulation for a Java chip-multiprocessor
TB StrÝm, M Schoeberl
2015 IEEE 18th International Symposium on Real-Time Distributed Computing†…, 2015
12015
Demonstration of a Time-predictable Flight Controller on a Multicore Processor
O Baris, S Majumder, TB StrÝm, A La Cour-Harbo, J SparsÝ, T Bak, ...
2019 IEEE 22nd International Symposium on Real-Time Distributed Computing†…, 2019
2019
Hardlock: Real-time multicore locking
TB StrÝm, J SparsÝ, M Schoeberl
Journal of Systems Architecture, 2019
2019
A lock circuit for a multi-core processor
TB StrÝm
WO Patent 2,015,132,293, 2015
2015
IEEE ISORC 2019 Secondary Reviewers
R Ant„o, O Baris, P Bartolomeu, Y Barve, M Becker, K Bletsas, JH Cheng, ...
ISORC 2018
A Lund, U Brinkschulte, TB StrÝm, M Schoeberl, S Ramanathan, ...
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