| The international exascale software project roadmap J Dongarra, P Beckman, T Moore, P Aerts, G Aloisio, JC Andre, D Barkai, ... International Journal of High Performance Computing Applications 25 (1), 3-60, 2011 | 730 | 2011 |
| A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. A González, C Aliagas, M Valero International Conference on Supercomputing, 338-347, 1995 | 372 | 1995 |
| Multiple-banked register file architectures JL Cruz, A González, M Valero, NP Topham ACM SIGARCH Computer Architecture News 28 (2), 316-325, 2000 | 340 | 2000 |
| Hardware support for WCET analysis of hard real-time multicore systems M Paolieri, E Quiñones, FJ Cazorla, G Bernat, M Valero ACM SIGARCH Computer Architecture News 37 (3), 57-68, 2009 | 295 | 2009 |
| Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors TY Morad, UC Weiser, A Kolodnyt, M Valero, E Ayguade IEEE Computer Architecture Letters 5 (1), 14-17, 2006 | 219 | 2006 |
| Dynamically controlled resource allocation in SMT processors FJ Cazorla, A Ramirez, M Valero, E Fernandez Proceedings of the 37th annual IEEE/ACM International Symposium on …, 2004 | 203 | 2004 |
| Discrete optimization problem in local networks and data alignment MA Fiol, JLA Yebra, I Alegre, M Valero IEEE Transactions on Computers, 702-713, 1987 | 188 | 1987 |
| Swing module scheduling: a lifetime-sensitive approach J Llosa, A González, E Ayguadé, M Valero Proceedings of the 1996 Conference on Parallel Architectures and Compilation …, 1996 | 174 | 1996 |
| Bandwidth of crossbar and multiple-bus connections for multiprocessors T Lang, M Valero Cortés, I Alegre de Miguel IEEE Transactions on Computers 100 (12), 1227-1234, 1982 | 172 | 1982 |
| An analyzable memory controller for hard real-time CMPs M Paolieri, E Quinones, FJ Cazorla, M Valero IEEE Embedded Systems Letters 1 (4), 86-90, 2009 | 167 | 2009 |
| Supercomputing with commodity CPUs: Are mobile SoCs ready for HPC? N Rajovic, PM Carpenter, I Gelado, N Puzovic, A Ramirez, M Valero Proceedings of the International Conference on High Performance Computing …, 2013 | 156 | 2013 |
| Fuzzy memoization for floating-point multimedia applications C Alvarez, J Corbal, M Valero IEEE Transactions on Computers 54 (7), 922-927, 2005 | 156 | 2005 |
| Virtual-physical registers A Gonzalez, J Gonzalez, M Valero Proceedings 1998 Fourth International Symposium on High-Performance Computer …, 1998 | 154 | 1998 |
| Out-of-order commit processors A Cristal, D Ortega, J Llosa, M Valero 10th International Symposium on High Performance Computer Architecture (HPCA …, 2004 | 152 | 2004 |
| Eliminating cache conflict misses through XOR-based placement functions A González, M Valero, N Topham, JM Parcerisa International Conference on Supercomputing, 76-83, 1997 | 149 | 1997 |
| EazyHTM: eager-lazy hardware transactional memory S Tomić, C Perfumo, C Kulkarni, A Armejach, A Cristal, O Unsal, T Harris, ... Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 142 | 2009 |
| Enabling preemptive multiprogramming on GPUs I Tanasic, I Gelado, J Cabezas, A Ramirez, N Navarro, M Valero 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014 | 139 | 2014 |
| Improving cache management policies using dynamic reuse distances N Duong, D Zhao, T Kim, R Cammarota, M Valero, AV Veidenbaum 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 389-400, 2012 | 139 | 2012 |
| Partitioning: an essential step in mapping algorithms into systolic array processors JJ Navarro Guerrero, JM Llaberia Griñó, M Valero Cortés Computer 20 (7), 77-89, 1987 | 139 | 1987 |
| Task superscalar: An out-of-order task pipeline Y Etsion, F Cabarcas, A Rico, A Ramirez, RM Badia, E Ayguade, ... 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 89-100, 2010 | 129 | 2010 |
Eduard AyguadeUniversitat Politecnica de Catalunya (UPC) and Barcelona Supercomputing Center (BSC)Verified email at ac.upc.edu
