Frank Hannig
TitleCited byYear
A highly parameterizable parallel processor array architecture
D Kissler, F Hannig, A Kupriyanov, J Teich
2006 IEEE International Conference on Field Programmable Technology, 105-112, 2006
852006
PARO: Synthesis of hardware accelerators for multi-dimensional dataflow-intensive applications
F Hannig, H Ruckdeschel, H Dutta, J Teich
International Workshop on Applied Reconfigurable Computing, 287-293, 2008
732008
HIPAcc: A Domain-Specific Language and Compiler for Image Processing
R Membarth, O Reiche, F Hannig, J Teich, M Körner, W Eckert
IEEE Transactions on Parallel and Distributed Systems 27 (1), 210-224, 2015
682015
Invasive tightly-coupled processor arrays: A domain-specific architecture/compiler co-design approach
F Hannig, V Lari, S Boppu, A Tanase, O Reiche
ACM Transactions on Embedded Computing Systems (TECS) 13 (4s), 133, 2014
662014
Generating device-specific GPU code for local operators in medical imaging
R Membarth, F Hannig, J Teich, M Körner, W Eckert
2012 IEEE 26th International Parallel and Distributed Processing Symposium …, 2012
472012
ExaStencils: Advanced stencil-code engineering
C Lengauer, S Apel, M Bolten, A Größlinger, F Hannig, H Köstler, U Rüde, ...
European Conference on Parallel Processing, 553-564, 2014
462014
Resource-aware programming and simulation of MPSoC architectures through extension of X10
F Hannig, S Roloff, G Snelting, J Teich, A Zwinkau
Proceedings of the 14th International Workshop on Software and Compilers for …, 2011
452011
FPGAs for Software Programmers
D Koch, F Hannig, D Ziener
Springer, 2016
442016
ExaSlang: A domain-specific language for highly scalable multigrid solvers
C Schmitt, S Kuckuk, F Hannig, H Köstler, J Teich
2014 Fourth International Workshop on Domain-Specific Languages and High …, 2014
412014
Code generation from a domain-specific language for C-based HLS of hardware accelerators
O Reiche, M Schmid, F Hannig, R Membarth, J Teich
Proceedings of the 2014 International Conference on Hardware/Software …, 2014
382014
Code generation for embedded heterogeneous architectures on Android
R Membarth, O Reiche, F Hannig, J Teich
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
372014
Design space exploration for massively parallel processor arrays
F Hannig, J Teich
International Conference on Parallel Computing Technologies, 51-65, 2001
372001
Power density-aware resource management for heterogeneous tiled multicores
H Khdr, S Pagani, E Sousa, V Lari, A Pathania, F Hannig, M Shafique, ...
IEEE Transactions on Computers 66 (3), 488-501, 2016
332016
Decentralized dynamic resource management support for massively parallel processor arrays
V Lari, A Narovlyanskyy, F Hannig, J Teich
ASAP 2011-22nd IEEE International Conference on Application-specific Systems …, 2011
332011
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template.
D Kissler, F Hannig, A Kupriyanov, J Teich
ReCoSoC, 31-37, 2006
332006
Power-efficient reconfiguration control in coarse-grained dynamically reconfigurable architectures
D Kissler, A Strawetz, F Hannig, J Teich
Journal of Low Power Electronics 5 (1), 96-105, 2009
322009
Resource constrained and speculative scheduling of an algorithm class with run-time dependent conditionals
F Hannig, J Teich
Proceedings. 15th IEEE International Conference on Application-Specific …, 2004
312004
Regular mapping for coarse-grained reconfigurable architectures
F Hannig, H Dutta, J Teich
2004 IEEE International Conference on Acoustics, Speech, and Signal …, 2004
302004
Mapping of regular nested loop programs to coarse-grained reconfigurable arrays-constraints and methodology
F Hannig, H Dutta, J Teich
18th International Parallel and Distributed Processing Symposium, 2004 …, 2004
292004
An image processing library for C-based high-level synthesis
M Schmid, N Apelt, F Hannig, J Teich
2014 24th International Conference on Field Programmable Logic and …, 2014
282014
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Articles 1–20