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Nicholas J Fraser
Nicholas J Fraser
Email verificata su sydney.edu.au
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Citata da
Citata da
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Finn: A framework for fast, scalable binarized neural network inference
Y Umuroglu, NJ Fraser, G Gambardella, M Blott, P Leong, M Jahre, ...
Proceedings of the 2017 ACM/SIGDA international symposium on fieldá…, 2017
12042017
FINN-R An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
M Blott, TB Preu▀er, NJ Fraser, G Gambardella, K O’brien, Y Umuroglu, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-23, 2018
3982018
Syq: Learning symmetric quantization for efficient deep neural networks
J Faraone, N Fraser, M Blott, PHW Leong
Proceedings of the IEEE Conference on Computer Vision and Patterná…, 2018
1532018
LogicNets: Co-designed neural networks and circuits for extreme-throughput applications
Y Umuroglu, Y Akhauri, NJ Fraser, M Blott
2020 30th International Conference on Field-Programmable Logic andá…, 2020
962020
Scaling binarized neural networks on reconfigurable logic
NJ Fraser, Y Umuroglu, G Gambardella, M Blott, P Leong, M Jahre, ...
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming andá…, 2017
732017
Inference of quantized neural networks on heterogeneous all-programmable devices
TB Preu▀er, G Gambardella, N Fraser, M Blott
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 833-838, 2018
532018
Ps and qs: Quantization-aware pruning for efficient low latency neural network inference
B Hawks, J Duarte, NJ Fraser, A Pappalardo, N Tran, Y Umuroglu
Frontiers in Artificial Intelligence 4, 676564, 2021
452021
FAT: Training neural networks for reliable inference under hardware faults
U Zahid, G Gambardella, NJ Fraser, M Blott, K Vissers
2020 IEEE International Test Conference (ITC), 1-10, 2020
322020
Memory-efficient dataflow inference for deep CNNs on FPGA
L Petrica, T Alonso, M Kroes, N Fraser, S Cotofana, M Blott
2020 International Conference on Field-Programmable Technology (ICFPT), 48-55, 2020
292020
Quantizing convolutional neural networks for low-power high-throughput inference engines
SO Settle, M Bollavaram, P D'Alberto, E Delaye, O Fernandez, N Fraser, ...
arXiv preprint arXiv:1805.07941, 2018
292018
Accuracy to throughput trade-offs for reduced precision neural networks on reconfigurable logic
J Su, NJ Fraser, G Gambardella, M Blott, G Durelli, DB Thomas, ...
Applied Reconfigurable Computing. Architectures, Tools, and Applicationsá…, 2018
292018
Customizing low-precision deep neural networks for FPGAs
J Faraone, G Gambardella, D Boland, N Fraser, M Blott, PHW Leong
2018 28th International Conference on Field Programmable Logic andá…, 2018
262018
Evaluation of optimized CNNs on heterogeneous accelerators using a novel benchmarking approach
M Blott, NJ Fraser, G Gambardella, L Halder, J Kath, Z Neveu, ...
IEEE Transactions on Computers 70 (10), 1654-1669, 2020
212020
A low latency kernel recursive least squares processor using FPGA technology
Y Pang, S Wang, Y Peng, NJ Fraser, PHW Leong
2013 International Conference on Field-Programmable Technology (FPT), 144-151, 2013
212013
Compressing low precision deep neural networks using sparsity-induced regularization in ternary networks
J Faraone, N Fraser, G Gambardella, M Blott, PHW Leong
Neural Information Processing: 24th International Conference, ICONIP 2017á…, 2017
172017
A fully pipelined kernel normalised least mean squares processor for accelerated parameter optimisation
NJ Fraser, DJM Moss, JK Lee, S Tridgell, CT Jin, PHW Leong
2015 25th International Conference on Field Programmable Logic andá…, 2015
112015
Scaling neural network performance through customized hardware architectures on reconfigurable logic
M Blott, TB Preu▀er, N Fraser, G Gambardella, K O'Brien, Y Umuroglu, ...
2017 IEEE International Conference on Computer Design (ICCD), 419-422, 2017
102017
Radiation-Tolerant Deep Learning Processor Unit (DPU)-Based Platform Using Xilinx 20-nm Kintex UltraScale FPGA
P Maillard, YP Chen, J Vidmar, N Fraser, G Gambardella, M Sawant, ...
IEEE Transactions on Nuclear Science 70 (4), 714-721, 2022
92022
Fault-tolerant neural network accelerators with selective TMR
TG Bertoa, G Gambardella, NJ Fraser, M Blott, J McAllister
IEEE Design & Test 40 (2), 67-74, 2022
92022
System and method for implementing neural networks in integrated circuits
N Fraser, M Blott
US Patent 10,839,286, 2020
82020
Il sistema al momento non pu˛ eseguire l'operazione. Riprova pi¨ tardi.
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