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Wendy Elsasser
Wendy Elsasser
Unknown affiliation
Verified email at arm.com
Title
Cited by
Cited by
Year
The gem5 simulator: Version 20.0+
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
3212020
Morphable counters: Enabling compact integrity trees for low-overhead secure memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, JA Joao, MK Qureshi
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
1112018
Synergy: Rethinking secure-memory design for error-correcting memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, MK Qureshi
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
1042018
Memory organization for security and reliability
G Saileshwar, PS Ramrakhyani, WA Elsasser
US Patent 10,540,297, 2020
242020
Method and apparatus for scheduling in a non-uniform compute device
JC Beard, W Elsasser, E Van Hensbergen, S Diestelhorst
US Patent 10,552,152, 2020
182020
Apparatus and method of handling caching of persistent data
W Wang, S Diestelhorst, WA Elsasser, AL Sandberg, N Nikoleris
US Patent 10,642,743, 2020
162020
Counter integrity tree for memory security
PS Ramrakhyani, R Avanzi, WA Elsasser
US Patent 10,733,313, 2020
142020
The gem5 simulator: Version 20.0+. CoRR abs/2007.03152 (2020)
J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ...
arXiv preprint arXiv:2007.03152, 2020
142020
Method and apparatus for hardware management of multiple memory pools
A Pellegrini, K Sudan, A Saidi, WA Elsasser
US Patent 10,417,141, 2019
142019
Multi-tier cache placement mechanism
J Wang, PS Ramrakhyani, W Wang, WA Elsasser
US Patent 10,831,678, 2020
122020
Apparatus including a memory controller for controlling direct data transfer between first and second memory modules using direct transfer commands
A Hansson, WA Elsasser, MA Campbell
US Patent 10,339,050, 2019
92019
Integrating DRAM power-down modes in gem5 and quantifying their impact
R Jagtap, M Jung, W Elsasser, C Weis, A Hansson, N Wehn
Proceedings of the International Symposium on Memory Systems, 86-95, 2017
82017
Method and system for re-ordering bits in a memory system
W Elsasser, M Greenberg
US Patent 9,280,454, 2016
72016
Reducing data movement and energy in multilevel cache hierarchies without losing performance: Can you have it all?
J Wang, P Ramrakhyani, W Elsasser, LK John
2019 28th International Conference on Parallel Architectures and Compilation …, 2019
62019
RAMPART: RowHammer Mitigation and Repair for Server Memory Systems
SC Woo, W Elsasser, M Hamburg, E Linstadt, MR Miller, T Song, ...
Proceedings of the International Symposium on Memory Systems, 1-15, 2023
52023
Method and apparatus for reordering in a non-uniform compute device
JC Beard, W Elsasser, S Wang
US Patent 10,445,094, 2019
52019
Execution dependence extension (EDE): ISA support for eliminating fences
T Shull, I Vougioukas, N Nikoleris, W Elsasser, J Torrellas
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021
42021
Apparatus and method of handling caching of persistent data
W Wang, S Diestelhorst, WA Elsasser, AL Sandberg, N Nikoleris
US Patent App. 16/865,642, 2020
42020
Non-volatile memory on chip
JT Irby, WA Elsasser, M Bhargava, YK Chong, GMN Lattimore, JD Dodrill
US Patent 11,520,658, 2022
12022
DRAM CACHE TAG PROBING
SC Woo, MR Miller, T Song, W Elsasser, M Babaie
US Patent App. 18/665,319, 2024
2024
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