Igor Loi
Igor Loi
Verified email at unibo.it
TitleCited byYear
Design issues and considerations for low-cost 3-D TSV IC technology
G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ...
IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010
3262010
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
I Loi, S Mitra, TH Lee, S Fujita, L Benini
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided …, 2008
2112008
A fully-synthesizable single-cycle interconnection network for shared-l1 processor clusters
A Rahimi, I Loi, MR Kakoee, L Benini
2011 Design, Automation & Test in Europe, 1-6, 2011
1062011
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
I Loi, F Angiolini, L Benini
Proceedings of the 2nd international conference on Nano-Networks, 15, 2007
842007
Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices
M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (10 …, 2017
752017
Characterization and implementation of fault-tolerant vertical links for 3-D networks-on-chip
I Loi, F Angiolini, S Fujita, S Mitra, L Benini
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
692010
An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics
F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017
622017
An efficient distributed memory interface for many-core platform with 3D stacked DRAM
I Loi, L Benini
Proceedings of the Conference on Design, Automation and Test in Europe, 99-104, 2010
612010
Developing mesochronous synchronizers to enable 3D NoCs
I Loi, F Angiolini, L Benini
Proceedings of the conference on Design, automation and test in Europe, 1414 …, 2008
572008
A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology
D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ...
Solid-State Electronics 117, 170-184, 2016
492016
Neurostream: Scalable and energy efficient deep learning with smart memory cubes
E Azarkhish, D Rossi, I Loi, L Benini
IEEE Transactions on Parallel and Distributed Systems 29 (2), 420-434, 2017
402017
Exploration and optimization of 3-D integrated DRAM subsystems
C Weis, I Loi, L Benini, N Wehn
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
402013
PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision
F Conti, D Rossi, A Pullini, I Loi, L Benini
Journal of Signal Processing Systems 84 (3), 339-354, 2016
382016
PULP: A parallel ultra low power platform for next generation IoT applications
D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ...
2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015
372015
Power/performance exploration of single-core and multi-core processor approaches for biomedical signal processing
AY Dogan, D Atienza, A Burg, I Loi, L Benini
International Workshop on Power and Timing Modeling, Optimization and …, 2011
372011
Area and power modeling for networks-on-chip with layout awareness
P Meloni, I Loi, F Angiolini, S Carta, M Barbaro, L Raffo, L Benini
VLSI Design 2007, 2007
362007
Synthesis of low-overhead configurable source routing tables for network interfaces
I Loi, F Angiolini, L Benini
Proceedings of the Conference on Design, Automation and Test in Europe, 262-267, 2009
322009
193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing
D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ...
2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016
302016
Ultra-low-latency lightweight DMA for tightly coupled multi-core clusters
D Rossi, I Loi, G Haugou, L Benini
Proceedings of the 11th ACM Conference on Computing Frontiers, 15, 2014
282014
High performance AXI-4.0 based interconnect for extensible smart memory cubes
E Azarkhish, D Rossi, I Loi, L Benini
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
272015
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