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Basant Kumar Mohanty
Basant Kumar Mohanty
Professor, Electronics and Telecommunication Engineering, Sambalpur University Institute of
Verified email at suiit.ac.in
Title
Cited by
Cited by
Year
Efficient integer DCT architectures for HEVC
PK Meher, SY Park, BK Mohanty, KS Lim, C Yeo
IEEE Transactions on Circuits and systems for Video Technology 24 (1), 168-178, 2013
2352013
Area–delay–power efficient carry-select adder
BK Mohanty, SK Patel
IEEE transactions on circuits and systems II: express briefs 61 (6), 418-422, 2014
1812014
A high-performance energy-efficient architecture for FIR adaptive filter based on new distributed arithmetic formulation of block LMS algorithm
BK Mohanty, PK Meher
IEEE transactions on signal processing 61 (4), 921-932, 2012
1412012
FPGA implementation of orthogonal matching pursuit for compressive sensing reconstruction
H Rabah, A Amira, BK Mohanty, S Almaadeed, PK Meher
IEEE Transactions on very large scale integration (VLSI) Systems 23 (10 …, 2014
1262014
A high-performance FIR filter architecture for fixed and reconfigurable applications
BK Mohanty, PK Meher
IEEE transactions on very large scale integration (VLSI) systems 24 (2), 444-452, 2015
1232015
Memory efficient modular VLSI architecture for highthroughput and low-latency implementation of multilevel lifting 2-D DWT
BK Mohanty, PK Meher
IEEE Transactions on signal processing 59 (5), 2072-2084, 2011
972011
Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT
BK Mohanty, PK Meher
IEEE Transaction on Circuit and System for Video Technology, 23 (2), 353-363, 2013
892013
Area-and power-efficient architecture for high-throughput implementation of lifting 2-D DWT
BK Mohanty, A Mahajan, PK Meher
IEEE transactions on circuits and systems ii: express briefs 59 (7), 434-438, 2012
762012
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters
BK Mohanty, PK Meher, S Al-Maadeed, A Amira
IEEE, 2013
592013
Efficient VLSI architecture for decimation-in-time fast Fourier transform of real-valued data
PK Meher, BK Mohanty, SK Patel, S Ganguly, T Srikanthan
IEEE Transactions on circuits and systems I: regular papers 62 (12), 2836-2845, 2015
432015
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic
BK Mohanty, PK Meher, SK Singhal, MNS Swamy
Integration 54, 37-46, 2016
422016
Hardware-efficient systolic-like modular design for two-dimensional discrete wavelet transform
PK Meher, BK Mohanty, JC Patra
IEEE Transactions on Circuits and Systems II: Express Briefs 55 (2), 151-155, 2008
352008
LUT optimization for distributed arithmetic-based block least mean square adaptive filter
BK Mohanty, PK Meher, SK Patel
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015
332015
FPGA implementation of LMS-based FIR adaptive filter for real time digital signal processing applications
C Safarian, T Ogunfunmi, WJ Kozacky, BK Mohanty
2015 IEEE International Conference on Digital Signal Processing (DSP), 1251-1255, 2015
282015
Efficient multiplierless designs for 1-D DWT using 9/7 filters based on distributed arithmetic
BK Mohanty, PK Meher
Proceedings of the 2009 12th International Symposium on Integrated Circuits …, 2009
232009
Low-area and low-power reconfigurable architecture for convolution-based 1-D DWT using 9/7 and 5/3 filters
PK Meher, BK Mohanty, MMS Swamy
2015 28th International Conference on VLSI Design, 327-332, 2015
222015
Cost-effective novel flexible cell-level systolic architecture for high throughput implementation of 2-D FIR filters
BK Mohanty, PK Meher
IEE Proceedings-Computers and Digital Techniques 143 (6), 436-439, 1996
221996
Modified PEB formulation for hardware-efficient fixed-width booth multiplier
BK Mohanty, V Tiwari
Circuits, Systems, and Signal Processing 33, 3981-3994, 2014
212014
Delayed block LMS algorithm and concurrent architecture for high-speed implementation of adaptive FIR filters
BK Mohanty, PK Meher
TENCON 2008-2008 IEEE Region 10 Conference, 1-5, 2008
212008
Area–delay–energy efficient vlsi architecture for scalable in-place computation of fft on real data
BK Mohanty, PK Meher
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (3), 1042-1050, 2018
192018
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