| A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference L Magnelli, F Crupi, P Corsonello, C Pace, G Iannaccone IEEE Journal of Solid-State Circuits 46 (2), 465-474, 2010 | 332 | 2010 |
| Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier L Magnelli, FA Amoroso, F Crupi, G Cappuccino, G Iannaccone International Journal of Circuit Theory and Applications 42 (9), 967-977, 2014 | 114 | 2014 |
| A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity L Magnelli, F Crupi, P Corsonello, G Iannaccone International Journal of Circuit Theory and Applications 43 (4), 421-426, 2015 | 7 | 2015 |
| Performance and reliability of ultra-thin oxide nMOSFETs under variable body bias F Crupi, L Magnelli, P Falbo, M Lanuzza, M Nafría, R Rodríguez Microelectronic engineering 84 (9-10), 1947-1950, 2007 | 5 | 2007 |
| Subthreshold design of ultra low-power analog modules L Magnelli | | 2012 |
| Metodologie di Polarizzazione del Substrato di Dispositivi CMOS per la Riduzione del Ritardo e della Potenza Dissipata L Magnelli | | 2005 |
Giuseppe IannacconeUniversity of Pisa, ItalyVerified email at unipi.it
Giuseppe IannacconeUniversity of Pisa, ItalyVerified email at unipi.it