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Rebecca Sejung Park
Rebecca Sejung Park
Electrical Engineering, Stanford University
Verified email at stanford.edu
Title
Cited by
Cited by
Year
Three-dimensional integration of nanotechnologies for computing and data storage on a single chip
MM Shulaker, G Hills, RS Park, RT Howe, K Saraswat, HSP Wong, S Mitra
Nature 547 (7661), 74-78, 2017
7132017
Hysteresis in carbon nanotube transistors: measurement and analysis of trap density, energy level, and spatial distribution
RS Park, MM Shulaker, G Hills, L Suriyasena Liyanage, S Lee, A Tang, ...
ACS nano 10 (4), 4599-4608, 2016
842016
Hysteresis-free carbon nanotube field-effect transistors
RS Park, G Hills, J Sohn, S Mitra, MM Shulaker, HSP Wong
ACS nano 11 (5), 4785-4791, 2017
612017
Low-temperature side contact to carbon nanotube transistors: Resistance distributions down to 10 nm contact length
G Pitner, G Hills, JP Llinas, KM Persson, R Park, J Bokor, S Mitra, ...
Nano letters 19 (2), 1083-1089, 2019
542019
Negative capacitance carbon nanotube FETs
T Srimani, G Hills, MD Bishop, U Radhakrishna, A Zubair, RS Park, ...
IEEE Electron Device Letters 39 (2), 304-307, 2017
502017
TRIG: Hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs
G Hills, D Bankman, B Moons, L Yang, J Hillard, A Kahng, R Park, ...
Proceedings of the 55th Annual Design Automation Conference, 1-10, 2018
132018
Molybdenum oxide on carbon nanotube: Doping stability and correlation with work function
RS Park, HJK Kim, G Pitner, C Neumann, S Mitra, HSP Wong
Journal of Applied Physics 128 (4), 2020
72020
Heterogeneous 3D nano-systems: The N3XT approach?
D Rich, A Bartolo, C Gilardo, B Le, H Li, R Park, RM Radway, ...
NANO-CHIPS 2030: On-Chip AI for an Efficient Data-Driven World, 127-151, 2020
52020
High-speed emerging memories for AI hardware accelerators
A Lu, J Lee, TH Kim, MAU Karim, RS Park, H Simka, S Yu
Nature Reviews Electrical Engineering 1 (1), 24-34, 2024
22024
Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods
S Yun, I Hwang, JO Gunho, J Yim, H Byounghak, K Seo, M He, J Park, ...
US Patent App. 17/554,483, 2023
12023
3d stacked field-effect transistor device with pn junction structure
M He, M Saremi, R Park, MAUL Karim, H Simka, S Park, K Myungil, K Kim, ...
US Patent App. 17/984,025, 2024
2024
3dsfet standard cell architecture with source-drain junction isolation
M He, M Saremi, R Park, MAUL Karim, H Simka, S Park, K Myungil, K Kim, ...
US Patent App. 17/984,042, 2024
2024
Fully aligned via integration with selective catalyzed vapor phase grown materials
M He, H Simka, R Park
US Patent App. 18/332,149, 2023
2023
Fully aligned via integration with selective catalyzed vapor phase grown materials
M He, H Simka, R Park
US Patent 11,705,363, 2023
2023
Methods of forming integrated circuit devices including stacked transistors and integrated circuit devices formed by the same
M He, J Park, M Saremi, R Park, H Simka, HA Daewon
US Patent App. 17/677,329, 2023
2023
Nanosheet transistor devices and related fabrication methods
M He, J Park, C Ahn, M Saremi, R Park, H Simka, HA Daewon
US Patent App. 17/679,465, 2023
2023
Understanding and Manipulating Charges Surrounding Carbon Nanotubes: A Step Towards High-performance Computing with Carbone Nanotube Transistors
R Park
Stanford University, 2020
2020
Understanding the physics that causes hysteresis in carbon nanotube transistors, a key step toward high performance and energy-efficiency
R Park
APS March Meeting Abstracts 2017, A31. 001, 2017
2017
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