Gabriele Sereni
TitleCited byYear
A New Physical Method Based onSimulations for the Characterization of the Interfacial and Bulk Defect Density in High-/III-V MOSFETs
G Sereni, L Vandelli, D Veksler, L Larcher
IEEE Transactions on Electron Devices 62 (3), 705-712, 2015
Extraction of the Defect Distributions in DRAM Capacitor UsingandSensitivity Maps
G Sereni, L Larcher, B Kaczer, MI Popovici
IEEE Electron Device Letters 37 (10), 1280-1283, 2016
A novel technique exploiting C–V, G–V and I–V simulations to investigate defect distribution and native oxide in high-κ dielectrics for III–V MOSFETs
G Sereni, L Larcher, L Vandelli, D Veksler, T Kim, D Koh, G Bersuker
Microelectronic Engineering 147, 281-284, 2015
A new method for extracting interface state and border trap densities in high-k/III-V MOSFETs
G Sereni, L Vandelli, L Larcher, L Morassi, D Veksler, G Bersuker
2014 IEEE International Reliability Physics Symposium, 2C. 3.1-2C. 3.6, 2014
Low leakage stoichiometric SrTiO3 dielectric for advanced metal–insulator–metal capacitors
M Popovici, B Kaczer, VV Afanas' Ev, G Sereni, L Larcher, A Redolfi, ...
physica status solidi (RRL)–Rapid Research Letters 10 (5), 420-425, 2016
Substrate and temperature influence on the trap density distribution in high-k III-V MOSFETs
G Sereni, L Vandelli, R Cavicchioli, L Larcher, D Veksler, G Bersuker
2015 IEEE International Reliability Physics Symposium, 2E. 6.1-2E. 6.5, 2015
Characterization and Modeling of Low-Cost Contact-Mode Triboelectric Devices for Energy Harvesting
A Bertacchini, M Lasagni, G Sereni, L Larcher, P Pavan
IECON 2018-44th Annual Conference of the IEEE Industrial Electronics Society …, 2018
Spettroscopia dei difetti atomici nei materiali ad alta permittivitą elettrica per dispositivi CMOS e beyond CMOS
Defect Spectroscopy and Engineering for Nanoscale Electron Device Applications: A Novel Simulation-Based Methodology
L Larcher, G Sereni, L Vandelli
ECS Transactions 72 (2), 167-177, 2016
Electrical defect spectroscopy and reliability prediction through a novel simulation-based methodology
L Larcher, G Sereni, A Padovani, L Vandelli
2016 International Symposium on VLSI Technology, Systems and Application …, 2016
Extraction of interface and border traps in beyond-Si devices by accounting for generation and recombination in the semiconductor
G Sereni, L Larcher
2015 IEEE International Integrated Reliability Workshop (IIRW), 46-51, 2015
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