| dMazeRunner: Executing perfectly nested loops on dataflow accelerators S Dave, Y Kim, S Avancha, K Lee, A Shrivastava ACM Transactions on Embedded Computing Systems (TECS) 18 (5s), 1-27, 2019 | 107 | 2019 |
| Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights S Dave, R Baghdadi, T Nowatzki, S Avancha, A Shrivastava, B Li Proceedings of the IEEE, 2021 | 97 | 2021 |
| RAMP: resource-aware mapping for CGRAs S Dave, M Balasubramanian, A Shrivastava Proceedings of the 55th Annual Design Automation Conference, 127, 2018 | 94 | 2018 |
| LASER: A Hardware/Software Approach to Accelerate Complicated Loops on CGRAs M Balasubramanian, S Dave, A Shrivastava, R Jeyapaul Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018 …, 2018 | 25 | 2018 |
| dmazerunner: Optimizing convolutions on dataflow accelerators S Dave, A Shrivastava, Y Kim, S Avancha, K Lee ICASSP 2020-2020 IEEE International Conference on Acoustics, Speech and …, 2020 | 21 | 2020 |
| CCF: A CGRA Compilation Framework S Dave, A Shrivastava | 19* | |
| Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems S Dave, A Marchisio, MA Hanif, A Guesmi, A Shrivastava, I Alouani, ... 2022 IEEE 40th VLSI Test Symposium (VTS), 1-14, 2022 | 16 | 2022 |
| URECA: A Compiler Solution to Manage Unified Register File for CGRAs S Dave, M Balasubramanian, A Shrivastava Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018 …, 2018 | 12 | 2018 |
| Ramp: Resource-aware mapping for cgras. In 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) S Dave, M Balasubramanian, A Shrivastava IEEE, 2018 | 11 | 2018 |
| SPX64: A Scratchpad Memory for General-purpose Microprocessors A Singh, S Dave, P Zardoshti, R Brotzman, C Zhang, X Guo, ... ACM Transactions on Architecture and Code Optimization (TACO) 18 (1), 1-26, 2020 | 9 | 2020 |
| Hybrid and efficient approach to accelerate complicated loops on coarse-grained reconfigurable arrays (cgra) accelerators M Balasubramanian, S Dave, A Shrivastava, R Jeyapaul US Patent App. 16/172,254, 2020 | 8 | 2020 |
| Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis S Dave, T Nowatzki, A Shrivastava Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 6 | 2023 |
| Design Space Description Language for Automated and Comprehensive Exploration of Next-Gen Hardware Accelerators S Dave, A Shrivastava Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), 2022 | 6 | 2022 |
| Derivation of Transfer Function Model based on Miniaturized Cryocooler Behavior J Bhatt, S Dave, M Mehta, N Upadhyay INROADS- An International Journal of Jaipur National University 5 (1s), 336-340, 2016 | 6 | 2016 |
| Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level B Ranjbar, F Klemme, PR Genssler, H Amrouch, J Jung, S Dave, H So, ... 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-10, 2023 | 2 | 2023 |
| Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs BR Willis, A Shrivastava, J Mack, S Dave, C Chakrabarti, J Brunhaver IEEE Transactions on Computers, 2023 | 1 | 2023 |
| Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures S Dave, A Shrivastava Semiconductor Research Corporation (SRC) Techcon, 2023 | 1 | 2023 |
| Systems and methods for agile and explainable optimization of efficient hardware/software codesigns for domain-specific computing systems using bottleneck analysis S Dave, A Shrivastava, T Nowatzki US Patent App. 18/485,811, 2024 | | 2024 |
| An Agile Methodology for Designing Efficient Domain-Specific Architectures S Dave Arizona State University, 2024 | | 2024 |
| CODES+ ISSS 2016 STEERING COMMITTEE R Bergamaschi, F Catthoor, K Choi, P Chou, G DeMicheli, N Dutt, P Eles, ... | | |
Aviral ShrivastavaArizona State UniversityVerified email at asu.edu
