Jacob Leverich
Jacob Leverich
PhD in Computer Science, Stanford University
Verified email at cs.stanford.edu - Homepage
TitleCited byYear
The case for RAMClouds: scalable high-performance storage entirely in DRAM
J Ousterhout, P Agrawal, D Erickson, C Kozyrakis, J Leverich, D Mazičres, ...
ACM SIGOPS Operating Systems Review 43 (4), 92-105, 2010
5962010
On the energy (in) efficiency of hadoop clusters
J Leverich, C Kozyrakis
ACM SIGOPS Operating Systems Review 44 (1), 61-65, 2010
4512010
The magazine archive includes every article published in Communications of the ACM for over the past 50 years.
J Ousterhout, P Agrawal, D Erickson, C Kozyrakis, J Leverich, D Mazičres, ...
Communications of the ACM 54 (7), 121-130, 2011
1942011
Reconciling high server utilization and sub-millisecond quality-of-service
J Leverich, C Kozyrakis
Proceedings of the Ninth European Conference on Computer Systems, 4, 2014
1782014
Power management of datacenter workloads using per-core power gating
J Leverich, M Monchiero, V Talwar, P Ranganathan, C Kozyrakis
IEEE Computer Architecture Letters 8 (2), 48-51, 2009
1462009
Comparing memory systems for chip multiprocessors
J Leverich, H Arakida, A Solomatnikov, A Firoozshahian, M Horowitz, ...
ACM SIGARCH Computer Architecture News 35 (2), 358-368, 2007
1392007
Future scaling of processor-memory interfaces
JH Ahn, NP Jouppi, C Kozyrakis, J Leverich, RS Schreiber
Proceedings of the Conference on High Performance Computing Networking …, 2009
1242009
Multicore DIMM: An energy efficient memory module with independently controlled DRAMs
JH Ahn, J Leverich, R Schreiber, NP Jouppi
IEEE Computer Architecture Letters 8 (1), 5-8, 2008
1092008
Improving system energy efficiency with memory rank subsetting
JH Ahn, NP Jouppi, C Kozyrakis, J Leverich, RS Schreiber
ACM Transactions on Architecture and Code Optimization (TACO) 9 (1), 4, 2012
382012
Independently controlled virtual memory devices in memory modules
JH Ahn, NP Jouppi, JB Leverich
US Patent 8,788,747, 2014
222014
Comparative evaluation of memory models for chip multiprocessors
J Leverich, H Arakida, A Solomatnikov, A Firoozshahian, M Horowitz, ...
ACM Transactions on Architecture and Code Optimization (TACO) 5 (3), 12, 2008
172008
Dynamic utilization of power-down modes in multi-core memory modules
JH Ahn, NP Jouppi, JB Leverich, RS Schreiber
US Patent 8,812,886, 2014
132014
Future scaling of datacenter power-efficiency
JB Leverich
Stanford University, 2014
102014
Evaluating impact of manageability features on device performance
J Leverich, V Talwar, P Ranganathan, C Kozyrakis
2010 International Conference on Network and Service Management, 426-430, 2010
22010
Integrated circuit package
M Monchiero, JB Leverich, P Ranganathan, NP Jouppi, V Talwar
US Patent 8,907,462, 2014
2014
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