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Mehdi Alipour
Mehdi Alipour
Uppsala University
Verified email at ericsson.com
Title
Cited by
Cited by
Year
Non-speculative load-load reordering in tso
A Ros, TE Carlson, M Alipour, S Kaxiras
ACM SIGARCH Computer Architecture News 45 (2), 187-200, 2017
332017
Ghost loads: What is the cost of invisible speculation?
C Sakalis, M Alipour, A Ros, A Jimborean, S Kaxiras, M Själander
Proceedings of the 16th ACM International Conference on Computing Frontiers …, 2019
322019
Freeway: Maximizing MLP for slice-out-of-order execution
R Kumar, M Alipour, D Black-Schaffer
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
232019
Design Space Exploration to Find the Optimum Cache and Register File Size for Embedded Applications
M Alipour, ME Salehi
9th Int'l Conf. Embedded Systems and Applications, ESA'11, las vegas, USA …, 2012
172012
Delay and bypass: Ready and criticality aware instruction scheduling in out-of-order processors
M Alipour, S Kaxiras, D Black-Schaffer, R Kumar
2020 IEEE International Symposium on High Performance Computer Architecture …, 2020
162020
Exploring the performance limits of out-of-order commit
M Alipour, TE Carlson, S Kaxiras
Proceedings of the Computing Frontiers Conference, 211-220, 2017
162017
Arvind,“
S Zhang, M Vijayaraghavan, A Wright, M Alipour
Constructing a weak memory model,” in ISCA, 2018
152018
Fiforder microarchitecture: Ready-aware instruction scheduling for ooo processors
M Alipour, R Kumar, S Kaxiras, D Black-Schaffer
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 716-721, 2019
112019
Cache power and performance tradeoffs for embedded applications
M Alipour, ME Salehi, K Moshari
2011 IEEE International Conference on Computer Applications and Industrial …, 2011
102011
Performance per power optimum cache architecture for embedded applications, a design space exploration
M Alipour, K Moshari, MR Bagheri
2011 IEEE 2nd International Conference on Networked Embedded Systems for …, 2011
82011
Multi objective design space exploration of cache for embedded applications
M Alipour, H Taghdisi, SH Sadeghzadeh
2012 25th IEEE Canadian Conference on Electrical and Computer Engineering …, 2012
72012
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors. In 2019 Design, Automation & Test in Europe Conference & Exhibition (Florence, Italy)(DATE …
M Alipour, R Kumar, S Kaxiras, D Black-Schaffer
52019
Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications
M Alipour, H Taghdisi
International Journal of Embedded Systems and Applications (IJESA) Vol.2 …, 2012
42012
Maximizing limited resources: a limit-based study and taxonomy of out-of-order commit
M Alipour, TE Carlson, D Black-Schaffer, S Kaxiras
Journal of Signal Processing Systems 91, 379-397, 2019
32019
Constructing a weak memory model
S Zhang, M Vijayaraghavan, A Wright, M Alipour
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
32018
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores
R Kumar, M Alipour, D Black-Schaffer
ACM Transactions on Architecture and Code Optimization (TACO) 19 (2), 1-28, 2022
12022
A taxonomy of out-of-order instruction commit
M Alipour, TE Carlson, S Kaxiras
2017 IEEE International Symposium on Performance Analysis of Systems and …, 2017
12017
Apparatus and Method for Simultaneous Multithreaded Instruction Scheduling in a Microprocessor
M Alipour, F Dahlgren
US Patent App. 18/031,070, 2023
2023
Apparatus and method for identifying and prioritizing certain instructions in a microprocessor instruction pipeline
M Alipour, A Hunt, F Dahlgren
US Patent App. 17/326,972, 2022
2022
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores
R Kumar, M Alipour, D Black-Schaffer
arXiv preprint arXiv:2201.00485, 2022
2022
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