Fearghal Morgan
Fearghal Morgan
University of Galway
Verified email at - Homepage
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Scheme for interlocking line card to an address recognition engine to support plurality of routing and bridging protocols by using network information look-up database
F Morgan, J O'Callaghan, MJ Seaman, J Rigby, A Walton, UM Quinlan, ...
US Patent 5,524,254, 1996
Maintaining healthy population diversity using adaptive crossover, mutation, and selection
B McGinley, J Maher, C O'Riordan, F Morgan
IEEE Transactions on Evolutionary Computation 15 (5), 692-714, 2011
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations
S Carrillo, J Harkin, L McDaid, F Morgan, S Pande, S Cawley, B McGinley
IEEE Trans. on Parallel and Distributed Systems, 1-1, 2012
Address recognition engine with look-up database for storing network information
A Walton, UM Quinlan, SF Bryant, MJ Seaman, J Rigby, F Morgan, ...
US Patent 5,519,858, 1996
Xilinx Vivado High Level Synthesis: Case Studies
DO Loughlin, S Cawley, A Coffey, F Callaly, D Lyons, F Morgan
Irish Signals & Systems Conference 2014, 2014
A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks
J Harkin, F Morgan, L McDaid, S Hall, B McGinley, S Cawley
International Journal of Reconfigurable Computing 2009, 2009
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers
S Carrillo, J Harkin, L McDaid, S Pande, S Cawley, B McGinley, F Morgan
Neural networks 33, 42-57, 2012
Hardware spiking neural network prototyping and application
S Cawley, F Morgan, B McGinley, S Pande, L McDaid, S Carrillo, J Harkin
Genetic Programming and Evolvable Machines 12, 257-280, 2011
Review of pedestrian detection techniques in automotive far‐infrared video
P Hurney, P Waldron, F Morgan, E Jones, M Glavin
IET intelligent transport systems 9 (8), 824-832, 2015
Xilinx FPGA Implementation of a Pixel Processor for Object Detection Applications
P Mc Curry, L Kilmartin, F Morgan
Irish Signals and Systems Conference (ISSC 2000), 404-411, 2000
Spiking neural networks for breast cancer classification in a dielectrically heterogeneous breast
M O'Halloran, B McGinley, RC Conceicao, F Morgan, E Jones, M Glavin
Progress In Electromagnetics Research 113, 413-428, 2011
Remote FPGA lab for enhancing learning of digital systems
F Morgan, S Cawley, D Newell
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 5 (3), 1-13, 2012
Night-time pedestrian classification with histograms of oriented gradients-local binary patterns vectors
P Hurney, P Waldron, F Morgan, E Jones, M Glavin
IET Intelligent Transport Journal, 2014
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks
J Harkin, F Morgan, S Hall, P Dudek, T Dowrick, L McDaid
2008 international conference on field programmable logic and applications …, 2008
Modular neural tile architecture for compact embedded hardware spiking neural network
S Pande, F Morgan, S Cawley, T Bruintjes, G Smit, B McGinley, S Carrillo, ...
Neural processing letters 38, 131-153, 2013
Remote FPGA lab with interactive control and visualisation interface
F Morgan, S Cawley, F Callaly, S Agnew, P Rocke, M O'Halloran, N Drozd, ...
Field Programmable Logic and Applications (FPL), 2011 International …, 2011
High speed optical wavefront sensing with low cost FPGAs
K Kepa, D Coburn, J Dainty, F Morgan
Measurement science review 8 (4), 87-93, 2008
Hierarchical network-on-chip and traffic compression for spiking neural network implementations
S Carrillo, J Harkin, LJ McDaid, S Pande, S Cawley, B McGinley, ...
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 83-90, 2012
Fixed Latency On-Chip Interconnect for Hardware Spiking Neural Network Architectures
S Pande, F Morgan, G Smit, T Bruintjes, J Rutgers, B McGinley, S Cawley, ...
Parallel Computing, Special Issue on Novel On-Chip Parallel Architectures …, 2013
Serecon: A secure dynamic partial reconfiguration controller
K Kepa, F Morgan, K Kosciuszkiewicz, T Surmacz
Symposium on VLSI, 2008. ISVLSI'08. IEEE Computer Society Annual, 292-297, 2008
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