Jens Sparsø
TitleCited byYear
Principles of asynchronous circuit design: a systems perspective
J Sparsø, SB Furber
Springer Netherlands, 2001
1265*2001
A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip
T Bjerregaard, J Sparso
Design, Automation and Test in Europe, 2005. Proceedings, 1226-1231 Vol. 2, 2005
3922005
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
LS Nielsen, C Niessen, J Sparso, K Van Berkel
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 2 (4), 391-397, 1994
3211994
Renoc: A network-on-chip architecture with reconfigurable topology
MB Stensgaard, J Sparso
Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium …, 2008
1882008
Designing asynchronous circuits for low power: An IFIR filter bank for a digital hearing aid
LS Nielsen, J Sparso
Proceedings of the IEEE 87 (2), 268-281, 1999
1511999
Delay-insensitive multi-ring structures
J Sparso, J Staunstrup
Integration, the VLSI journal 15 (3), 313-340, 1993
1471993
Scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip
T Bjerregaard, J Sparso
11th IEEE International Symposium on Asynchronous Circuits and Systems, 34-43, 2005
1332005
T-CREST: Time-predictable multi-core architecture for embedded systems
M Schoeberl, S Abbaspour, B Akesson, N Audsley, R Capasso, J Garside, ...
Journal of Systems Architecture 61 (9), 449-471, 2015
1212015
Asynchronous Circuit Design—A Tutorial, copyright 2006
J Sparso
available from the Technical University of Denmark, Kgs. Lyngby, Denmark, 1-179, 0
117*
A statically scheduled time-division-multiplexed network-on-chip for real-time systems
M Schoeberl, F Brandner, J Sparsø, E Kasapaki
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip, 152-160, 2012
1092012
Design of delay insensitive circuits using multi-ring structures
J Sparsø, J Staunstrup, M Dantzer-Sørensen
European Design Automation Conference, 15-20, 1992
1091992
A network traffic generator model for fast network-on-chip simulation
S Mahadevan, F Angiolini, M Storgaard, RG Olsen, J Sparso, J Madsen
Proceedings of the conference on Design, Automation and Test in Europe …, 2005
882005
Implementation of guaranteed services in the MANGO clockless network-on-chip
T Bjerregaard, J Sparsø
IEE Proceedings-Computers and Digital Techniques 153 (4), 217-229, 2006
852006
An OCP compliant network adapter for GALS-based SoC design using the MANGO network-on-chip
T Bjerregaard, S Mahadevan, RG Olsen, J Sparso
2005 International Symposium on System-on-Chip, 171-174, 2005
762005
Argo: A real-time network-on-chip architecture with an efficient GALS implementation
E Kasapaki, M Schoeberl, RB Sørensen, C Müller, K Goossens, J Sparsø
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 479-492, 2015
712015
An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures
J Sparso, HN Jorgensen, E Paaske, S Pedersen, T Rubner-Petersen
IEEE journal of solid-state circuits 26 (2), 90-97, 1991
661991
Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip
T Bjerregaard, J Sparso
Norchip Conference, 2004. Proceedings, 269-272, 2004
602004
An area-efficient network interface for a TDM-based network-on-chip
J Sparsø, E Kasapaki, M Schoeberl
Proceedings of the Conference on Design, Automation and Test in Europe, 1044 …, 2013
442013
A low-power asynchronous data-path for a FIR filter bank
LS Nielsen, J Sparso
Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings …, 1996
43*1996
An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders
E Paaske, S Pedersen, J Sparsų
Integration, the VLSI journal 12 (1), 79-91, 1991
401991
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Articles 1–20