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Daniel Nagy
Daniel Nagy
Device Modeling Group, University of Glasgow
Verified email at glasgow.ac.uk
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Cited by
Year
FinFET versus gate-all-around nanowire FET: performance, scaling, and variability
D Nagy, G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, ...
IEEE Journal of the Electron Devices Society 6, 332-340, 2018
1942018
Benchmarking of FinFET, nanosheet, and nanowire FET architectures for future technology nodes
D Nagy, G Espineira, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane
IEEE Access 8, 53196-53202, 2020
692020
Quantum corrections based on the 2-D Schrödinger equation for 3-D finite element Monte Carlo simulations of nanoscaled FinFETs
J Lindberg, M Aldegunde, D Nagy, WG Dettmer, K Kalna, ...
IEEE Transactions on Electron Devices 61 (2), 423-429, 2014
472014
Comparison of fin-edge roughness and metal grain work function variability in InGaAs and Si FinFETs
N Seoane, G Indalecio, M Aldegunde, D Nagy, MA Elmessary, ...
IEEE Transactions on Electron Devices 63 (3), 1209-1216, 2016
462016
Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations
MA Elmessary, D Nagy, M Aldegunde, N Seoane, G Indalecio, J Lindberg, ...
Solid-State Electronics 128, 17-24, 2016
442016
Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET
G Espineira, D Nagy, G Indalecio, AJ Garcia-Loureiro, K Kalna, N Seoane
IEEE Electron Device Letters 40 (4), 510-513, 2019
342019
Metal grain granularity study on a gate-all-around nanowire FET
D Nagy, G Indalecio, AJ Garcia-Loureiro, MA Elmessary, K Kalna, ...
IEEE Transactions on Electron Devices 64 (12), 5263-5269, 2017
292017
3-D finite element Monte Carlo simulations of scaled Si SOI FinFET with different cross sections
D Nagy, MA Elmessary, M Aldegunde, R Valin, A Martinez, J Lindberg, ...
IEEE Transactions on Nanotechnology 14 (1), 93-100, 2014
232014
Impact of cross-sectional shape on 10-nm gate length InGaAs FinFET performance and variability
N Seoane, G Indalecio, D Nagy, K Kalna, AJ Garcia-Loureiro
IEEE Transactions on Electron Devices 65 (2), 456-462, 2018
222018
A multi-method simulation toolbox to study performance and variability of nanowire FETs
N Seoane, D Nagy, G Indalecio, G Espiñeira, K Kalna, A García-Loureiro
Materials 12 (15), 2391, 2019
212019
Anisotropic quantum corrections for 3-D finite-element Monte Carlo simulations of nanoscale multigate transistors
MA Elmessary, D Nagy, M Aldegunde, J Lindberg, WG Dettmer, D Períc, ...
IEEE Transactions on Electron Devices 63 (3), 933-939, 2016
182016
Impact of threshold voltage extraction methods on semiconductor device variability
G Espiñera, D Nagy, A García-Loureiro, N Seoane, G Indalecio
Solid-State Electronics 159, 165-170, 2019
122019
Simulation and modeling of novel electronic device architectures with NESS (nano-electronic simulation software): A modular nano TCAD simulation framework
C Medina-Bailon, T Dutta, A Rezaei, D Nagy, F Adamu-Lema, ...
Micromachines 12 (6), 680, 2021
92021
Nano-electronic simulation software (NESS): a novel open-source TCAD simulation environment
C Medina-Bailon, T Dutta, F Adamu-Lema, A Rezaei, D Nagy, ...
Journal of Microelectronic Manufacturing 3 (4), 2020
92020
Simulation study of scaled In0. 53Ga0. 47As and Si FinFETs for sub-16 nm technology nodes
N Seoane, M Aldegunde, D Nagy, MA Elmessary, G Indalecio, ...
Semiconductor Science and Technology 31 (7), 075005, 2016
92016
3D Schrödinger equation quantum corrected Monte Carlo and drift diffusion simulations of stacked nanosheet gate-all-around transistor
K Kalna, D Nagy, AJ García-Loureiro, N Seoane
IWCN, Wien: Institute for Microelectronics, TU Wien, 33-35, 2019
82019
Drift-diffusion versus Monte Carlo simulated ON-current variability in nanowire FETs
D Nagy, G Indalecio, AJ Garcia-Loureiro, G Espineira, MA Elmessary, ...
IEEE Access 7, 12790-12797, 2019
82019
Enhanced capabilities of the nano-electronic simulation software (ness)
C Medina-Bailon, O Badami, H Carrillo-Nunez, T Dutta, D Nagy, ...
2020 International Conference on Simulation of Semiconductor Processes and …, 2020
52020
Tcad simulation of novel semiconductor devices
T Dutta, C Medina-Bailon, A Rezaei, D Nagy, F Adamu-Lema, N Xeni, ...
2021 IEEE 14th International Conference on ASIC (ASICON), 1-4, 2021
32021
FoMPy: A figure of merit extraction tool for semiconductor device simulations
G Espiñeira, N Seoane, D Nagy, G Indalecio, AJ García-Loureiro
2018 Joint International EUROSOI Workshop and International Conference on …, 2018
32018
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