| BYOC: a" bring your own core" framework for heterogeneous-ISA research J Balkind, K Lim, M Schaffner, F Gao, G Chirkov, A Li, A Lavrov, ... Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020 | 52 | 2020 |
| OpenPiton at 5: A nexus for open and agile hardware design J Balkind, TJ Chang, PJ Jackson, G Tziantzioulis, A Li, F Gao, A Lavrov, ... IEEE Micro 40 (4), 22-31, 2020 | 17 | 2020 |
| SMAPPIC: Scalable multi-FPGA architecture prototype platform in the cloud G Chirkov, D Wentzlaff Proceedings of the 28th ACM International Conference on Architectural …, 2023 | 6 | 2023 |
| DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including … F Gao, TJ Chang, A Li, M Orenes-Vera, D Giri, PJ Jackson, A Ning, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 5 | 2023 |
| Seizing the bandwidth scaling of on-package interconnect in a post-Moore's law world G Chirkov, D Wentzlaff Proceedings of the 37th International Conference on Supercomputing, 410-422, 2023 | 4 | 2023 |
| CIFER: A Cache-Coherent 12nm 16mm 2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm 2 Synthesizable eFPGA A Li, TJ Chang, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... IEEE Solid-State Circuits Letters, 2023 | 2 | 2023 |
| CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA TJ Chang, A Li, F Gao, T Ta, G Tziantzioulis, Y Ou, M Wang, J Tu, K Xu, ... 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | 2 | 2023 |
