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Samuel Bayliss
Samuel Bayliss
Doctoral Prize Research Fellow, Imperial College London
Bestätigte E-Mail-Adresse bei imperial.ac.uk - Startseite
Titel
Zitiert von
Zitiert von
Jahr
High-level synthesis of dynamic data structures: A case study using Vivado HLS
F Winterstein, S Bayliss, GA Constantinides
2013 International conference on field-programmable technology (FPT), 362-365, 2013
1322013
FPGA-based K-means clustering using tree-based data structures
F Winterstein, S Bayliss, GA Constantinides
2013 23rd International Conference on Field programmable Logic and …, 2013
612013
An FPGA implementation of the simplex algorithm
S Bayliss, GA Constantinides, W Luk
2006 IEEE international conference on field programmable technology, 49-56, 2006
362006
MATCHUP: memory abstractions for heap manipulating programs
F Winterstein, K Fleming, HJ Yang, S Bayliss, G Constantinides
Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015
352015
Offline synthesis of online dependence testing: Parametric loop pipelining for HLS
J Liu, S Bayliss, GA Constantinides
2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015
342015
Optimizing SDRAM bandwidth for custom FPGA loop accelerators
S Bayliss, GA Constantinides
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
342012
Survey of domain-specific languages for FPGA computing
N Kapre, S Bayliss
2016 26th International Conference on Field Programmable Logic and …, 2016
262016
Polyhedral-based dynamic loop pipelining for high-level synthesis
J Liu, J Wickerson, S Bayliss, GA Constantinides
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
242017
Datapath synthesis for overclocking: Online arithmetic for latency-accuracy trade-offs
K Shi, D Boland, E Stott, S Bayliss, GA Constantinides
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
242014
Methodology for designing statically scheduled application-specific SDRAM controllers using constrained local search
S Bayliss, GA Constantinides
2009 International Conference on Field-Programmable Technology, 304-307, 2009
222009
Separation logic-assisted code transformations for efficient high-level synthesis
F Winterstein, S Bayliss, GA Constantinides
2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014
212014
SOAP: structural optimization of arithmetic expressions for high-level synthesis
X Gao, S Bayliss, GA Constantinides
2013 International Conference on Field-Programmable Technology (FPT), 112-119, 2013
202013
GPU vs FPGA: A comparative analysis for non-standard precision
UI Minhas, S Bayliss, GA Constantinides
International Symposium on Applied Reconfigurable Computing, 298-305, 2014
192014
Application specific memory access, reuse and reordering for SDRAM
S Bayliss, GA Constantinides
International Symposium on Applied Reconfigurable Computing, 41-52, 2011
112011
Separation logic for high-level synthesis
FJ Winterstein, SR Bayliss, GA Constantinides
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (2), 1-23, 2015
102015
Area implications of memory partitioning for high-level synthesis on FPGAs
L Gallo, A Cilardo, D Thomas, S Bayliss, GA Constantinides
2014 24th International Conference on Field Programmable Logic and …, 2014
102014
Vyasa: A high-performance vectorizing compiler for tensor convolutions on the Xilinx AI Engine
P Chatarasi, S Neuendorffer, S Bayliss, K Vissers, V Sarkar
2020 IEEE High Performance Extreme Computing Conference (HPEC), 1-10, 2020
52020
Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies
J Liu, J Wickerson, S Bayliss, GA Constantinides
2017 51st Asilomar Conference on Signals, Systems, and Computers, 126-130, 2017
32017
Compilation flow for a heterogeneous multi-core architecture
M Sivaraman, SA Gupta, A Sastry, R Surendran, PB James-Roxby, ...
US Patent 10,860,766, 2020
22020
Control and reconfiguration of data flow graphs on heterogeneous computing platform
CJ Hsu, SA Gupta, SR Bayliss, PB James-Roxby, RD Wittig, V Kathail
US Patent 10,802,807, 2020
22020
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