William Dally
TitleCited byYear
Route packets, not wires: on-chip inteconnection networks
WJ Dally, B Towles
Proceedings of the 38th annual Design Automation Conference, 684-689, 2001
Principles and practices of interconnection networks
WJ Dally, BP Towles
Elsevier, 2004
Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding
S Han, H Mao, WJ Dally
arXiv preprint arXiv:1510.00149, 2015
Deadlock-free message routing in multiprocessor interconnection networks
WJ Dally, CL Seitz
California Institute of Technology, 1988
SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and< 0.5 MB model size
FN Iandola, S Han, MW Moskewicz, K Ashraf, WJ Dally, K Keutzer
arXiv preprint arXiv:1602.07360, 2016
Learning both weights and connections for efficient neural network
S Han, J Pool, J Tran, W Dally
Advances in neural information processing systems, 1135-1143, 2015
Virtual-channel flow control
WJ Dally
IEEE Transactions on Parallel & Distributed Systems, 194-205, 1992
Performance analysis of k-ary n-cube interconnection networks
WJ Dally
IEEE transactions on Computers 39 (6), 775-785, 1990
Digital systems engineering
WJ Dally, WJ Dally, JW Poulton
Cambridge university press, 1998
The torus routing chip
WJ Dally, CL Seitz
Distributed computing 1 (4), 187-196, 1986
Exascale computing study: Technology challenges in achieving exascale systems
K Bergman, S Borkar, D Campbell, W Carlson, W Dally, M Denneau, ...
Defense Advanced Research Projects Agency Information Processing Techniques …, 2008
EIE: efficient inference engine on compressed deep neural network
S Han, X Liu, H Mao, J Pu, A Pedram, MA Horowitz, WJ Dally
ACM SIGARCH Computer Architecture News 44 (3), 243-254, 2016
Memory access scheduling
S Rixner, WJ Dally, UJ Kapasi, P Mattson, JD Owens
ACM SIGARCH Computer Architecture News 28 (2), 128-138, 2000
The GPU computing era
J Nickolls, WJ Dally
IEEE micro 30 (2), 56-69, 2010
Deadlock-free adaptive routing in multicomputer networks using virtual channels
WJ Dally, H Aoki
IEEE transactions on Parallel and Distributed Systems 4 (4), 466-475, 1993
A delay model and speculative architecture for pipelined routers
LS Peh, WJ Dally
Proceedings HPCA Seventh International Symposium on High-Performance …, 2001
Design tradeoffs for tiled CMP on-chip networks
J Balfour, WJ Dally
ACM International Conference on Supercomputing 25th Anniversary Volume, 390-401, 2006
Sequoia: Programming the memory hierarchy
K Fatahalian, DR Horn, TJ Knight, L Leem, M Houston, JY Park, M Erez, ...
Proceedings of the 2006 ACM/IEEE conference on Supercomputing, 83-es, 2006
Research challenges for on-chip interconnection networks
JD Owens, WJ Dally, R Ho, DN Jayasimha, SW Keckler, LS Peh
IEEE micro 27 (5), 96-108, 2007
The limitations to delay-insensitivity in asynchronous circuits
AJ Martin
Beauty is our business, 302-311, 1990
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