Yakun Sophia Shao
Yakun Sophia Shao
Assistant Professor of EECS, UC Berkeley
Verified email at berkeley.edu - Homepage
TitleCited byYear
Aladdin: A Pre-RTL, Power-Performance Accelerator Simulator Enabling Large Design Space Exploration of Customized Architectures
YS Shao, B Reagen, GY Wei, D Brooks
International Symposium on Computer Architecture (ISCA), 2014
1632014
Energy Characterization and Instruction-Level Energy Model of Intel’s Xeon Phi Processor
YS Shao, D Brooks
International Symposium on Low Power Electronics and Design (ISLPED), 2013
1052013
MachSuite: Benchmarks for Accelerator Design and Customized Architectures
B Reagen, R Adolf, YS Shao, GY Wei, D Brooks
IEEE International Symposium on Workload Characterization (IISWC), 2014
1012014
ISA-Independent Workload Characterization and its Implications for Specialized Architectures
YS Shao, D Brooks
International Symposium on Performance Analysis of Systems and Software …, 2013
562013
Co-Designing Accelerators and SoC Interfaces using gem5-Aladdin
YS Shao, SL Xi, V Srinivasan, GY Wei, D Brooks
International Symposium on Microarchitecture (MICRO), 2016
392016
The Aladdin Approach to Accelerator Design and Modeling
YS Shao, B Reagen, GY Wei, D Brooks
IEEE Micro, 2015
232015
Quantifying Acceleration: Power/Performance Trade-Offs of Application Kernels in Hardware
B Reagen, YS Shao, GY Wei, D Brooks
International Symposium on Low Power Electronics and Design (ISLPED), 2013
182013
Toward Cache-Friendly Hardware Accelerators
YS Shao, S Xi, V Srinivasan, GY Wei, D Brooks
HPCA Sensors and Cloud Architectures Workshop (SCAW), 2015
162015
Research infrastructures for hardware accelerators
YS Shao, D Brooks
Synthesis Lectures on Computer Architecture 10 (4), 1-99, 2015
122015
A modular digital VLSI flow for high-productivity SoC design
B Khailany, E Krimer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ...
2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), 1-6, 2018
72018
Power, Performance and Portability: System Design Considerations for Micro Air Vehicle Applications
YS Shao, J Porter, M Lyons, GY Wei, D Brooks
Advanced Computer Architecture and Compilation for Embedded Systems (ACACES), 2010
42010
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration
M Pellauer, YS Shao, J Clemons, N Crago, K Hegde, R Ventakesan, ...
International Conference on Architectural Support for Programming Languages …, 2019
32019
Stitch-X: An Accelerator Architecture for Exploiting Unstructured Sparsity in Deep Neural Networks
CE Lee, YS Shao, JF Zhang, A Parashar, J Emer, SW Keckler, Z Zhang
32018
Timeloop: A Systematic Approach to DNN Accelerator Evaluation
A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ...
International Symposium on Performance Analysis of Systems and Software (ISPASS), 2019
22019
Using dynamic dependence analysis to improve the quality of high-level synthesis designs
R Garibotti, B Reagen, YS Shao, GY Wei, D Brooks
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017
22017
Design and Modeling of Specialized Architectures
YS Shao
Harvard University, 2016
22016
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ...
2019 Symposium on VLSI Circuits, C300-C301, 2019
12019
Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis
R Garibotti, B Reagen, YS Shao, GY Wei, D Brooks
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (10), 1440-1444, 2018
12018
SNAP: A 1.67—21.55 TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS
JF Zhang, CE Lee, C Liu, YS Shao, SW Keckler, Z Zhang
2019 Symposium on VLSI Circuits, C306-C307, 2019
2019
Hardware Acceleration
M Kim, YS Shao
IEEE Micro 38 (6), 6-7, 2018
2018
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