Shidhartha Das
Title
Cited by
Cited by
Year
Razor: A low-power pipeline based on circuit-level timing speculation
D Ernst, NS Kim, S Das, S Pant, R Rao, T Pham, C Ziesler, D Blaauw, ...
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
16352003
RazorII: In situ error detection and correction for PVT and SER tolerance
S Das, C Tokunaga, S Pant, WH Ma, S Kalaiselvan, K Lai, DM Bull, ...
IEEE Journal of Solid-State Circuits 44 (1), 32-48, 2008
6992008
A self-tuning DVS processor using delay-error detection and correction
S Das, D Roberts, S Lee, S Pant, D Blaauw, T Austin, K Flautner, T Mudge
IEEE Journal of Solid-State Circuits 41 (4), 792-804, 2006
5522006
Razor: circuit-level correction of timing errors for low-power operation
D Ernst, S Das, S Lee, D Blaauw, T Austin, T Mudge, NS Kim, K Flautner
IEEE Micro 24 (6), 10-20, 2004
4932004
Razor II: In situ error detection and correction for PVT and SER tolerance
D Blaauw, S Kalaiselvan, K Lai, WH Ma, S Pant, C Tokunaga, S Das, ...
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
2552008
A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation
D Bull, S Das, K Shivashankar, GS Dasika, K Flautner, D Blaauw
IEEE Journal of Solid-State Circuits 46 (1), 18-31, 2011
244*2011
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation (vol 46, pg 18, 2011)
D Bull, S Das, K Shivashankar, GS Dasika, K Flautner, D Blaauw
IEEE JOURNAL OF SOLID-STATE CIRCUITS 46 (3), 705-705, 2011
183*2011
Circuit-level timing error tolerance for low-power DSP filters and transforms
PN Whatmough, S Das, DM Bull, I Darwazeh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (6), 989-999, 2013
682013
Harnessing voltage margins for energy efficiency in multicore CPUs
G Papadimitriou, M Kaliorakis, A Chatzidimitriou, D Gizopoulos, ...
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
632017
Reducing pipeline energy demands with local DVS and dynamic retiming
S Lee, S Das, T Pham, T Austin, D Blaauw, T Mudge
Proceedings of the 2004 international symposium on Low power electronics and …, 2004
492004
A low-power 1-ghz razor fir accelerator with time-borrow tracking pipeline and approximate error correction in 65-nm cmos
PN Whatmough, S Das, DM Bull
IEEE Journal of Solid-State Circuits 49 (1), 84-94, 2014
482014
A low-power 1-ghz razor fir accelerator with time-borrow tracking pipeline and approximate error correction in 65-nm cmos
PN Whatmough, S Das, DM Bull
IEEE Journal of Solid-State Circuits 49 (1), 84-94, 2014
482014
A triple core lock-step (TCLS) ARM® Cortex®-R5 processor for safety-critical and ultra-reliable applications
X Iturbe, B Venu, E Ozer, S Das
2016 46th Annual IEEE/IFIP International Conference on Dependable Systems …, 2016
472016
Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS
S Das, P Whatmough, D Bull
2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015
382015
Single event upset error detection within an integrated circuit
S Das, DT Blaauw, DM Bull
US Patent 8,185,812, 2012
352012
Error recover within processing stages of an integrated circuit
K Flautner, TM Austin, DT Blaauw, TN Mudge
US Patent 8,407,537, 2013
29*2013
Apparatus and method for adjusting a supply voltage based on a read result
D New, PD Hoxey, DM Bull, S Das
US Patent 7,876,634, 2011
28*2011
Power integrity analysis of a 28 nm dual-core arm cortex-a57 cluster using an all-digital power delivery monitor
PN Whatmough, S Das, Z Hadjilambrou, DM Bull
IEEE Journal of Solid-State Circuits 52 (6), 1643-1654, 2017
252017
Method and circuit for detection of a fault event
S Das, A Savanth, D Bull
US Patent 9,621,161, 2017
252017
Latching device and method
PAK Savanth, JE Myers, S Das
US Patent 9,734,895, 2017
242017
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