| Hardware/software tradeoffs for increased performance J Hennessy, N Jouppi, F Baskett, T Gross, J Gill ACM SIGPLAN Notices 17 (4), 2-11, 1982 | 250* | 1982 |
| Communications device for data processing system TR Ermolovich, RE Stewart, JS Leonard, DN Cutler US Patent 4,319,323, 1982 | 173 | 1982 |
| System and method for remote direct memory access without page locking by the operating system JS Leonard, D Gingold, LC Stewart US Patent 7,533,197, 2009 | 71 | 2009 |
| Remote DMA systems and methods for supporting synchronization of distributed processes in a multi-processor system using collective operations JS Leonard, LC Stewart, D Gingold US Patent App. 11/594,427, 2008 | 61 | 2008 |
| Apparatus and method for a pipelined central processing unit in a data processing system NC Wilhelm, JS Leonard US Patent 4,991,078, 1991 | 54 | 1991 |
| RDMA systems and methods for sending commands from a source node to a target node for local execution of commands at the target node JS Leonard, LC Stewart, D Gingold US Patent App. 11/594,443, 2008 | 37 | 2008 |
| Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors MC Mattina, C Ramey, B Jung, J Leonard US Patent 7,620,954, 2009 | 31 | 2009 |
| Floating point arithmetic system and method S Turrini, JS Leonard, NP Jouppi US Patent 4,999,803, 1991 | 30 | 1991 |
| Apparatus and method for synchronization of a coprocessor unit in a pipelined central processing unit NC Wilhelm, JS Leonard US Patent 4,943,915, 1990 | 27 | 1990 |
| System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel MH Reilly, N Godiwala, JS Leonard US Patent 7,773,616, 2010 | 26 | 2010 |
| System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels JS Leonard, MH Reilly, N Godiwala US Patent 7,773,618, 2010 | 16 | 2010 |
| Dynamically configurable signal processor and processor arrangement BC Johnson, C Basile, A Miron, NHE Weste, CJ Terman, J Leonard US Patent 5,034,907, 1991 | 15 | 1991 |
| System and method of multi-core cache coherency JS Leonard, MH Reilly WO Patent App. PCT/US2007/001,100, 2007 | 13 | 2007 |
| A 66-MHz DSP-augmented RAMDAC for smooth-shaded graphic applications J Leonard, N Weste, L Bodony, S Harston, R Meaney IEEE Journal of Solid-State Circuits 26 (3), 217-228, 1991 | 12 | 1991 |
| Systems and methods for remote direct memory access to processor caches for RDMA reads and writes MH Reilly, JS Leonard US Patent App. 11/594,447, 2008 | 9 | 2008 |
| A network fabric for scalable multiprocessor systems N Godiwala, J Leonard, M Reilly 2008 16th IEEE Symposium on High Performance Interconnects, 137-144, 2008 | 7 | 2008 |
| Large scale multi-processor system with a link-level interconnect providing in-order packet delivery N Godiwala, JS Leonard, MH Reilly, LC Stewart WO Patent App. PCT/US2007/082,867, 2007 | 7 | 2007 |
| Sicortex technical summary M Reilly, LC Stewart, J Leonard, D Gingold White paper, SiCortex, Dec, 2006 | 7 | 2006 |
| Computer system and method using a kautz-like digraph to interconnect computer nodes and having control back channel between nodes JS Leonard, MH Reilly, LC Stewart, W Taylor US Patent 7,751,344, 2010 | 6 | 2010 |
| Chunky binary multiplier and method of operation RA Eustace, JS Leonard US Patent 5,327,368, 1994 | 6 | 1994 |
Neil WesteUniversity of Adelaide, Macquarie UniversityEmail verificata su morsemicro.com
Neil WesteUniversity of Adelaide, Macquarie UniversityEmail verificata su morsemicro.com