| Scheduling and automatic parallelization A Darte, Y Robert, F Vivien Springer Science & Business Media, 2012 | 280 | 2012 |
| Multi-dimensional rankings, program termination, and complexity bounds of flowchart programs C Alias, A Darte, P Feautrier, L Gonnord Static Analysis: 17th International Symposium, SAS 2010, Perpignan, France …, 2010 | 235 | 2010 |
| On the complexity of loop fusion A Darte 1999 International Conference on Parallel Architectures and Compilation …, 1999 | 212 | 1999 |
| Lattice-based memory allocation A Darte, R Schreiber, G Villard Proceedings of the 2003 international conference on Compilers, architecture …, 2003 | 184 | 2003 |
| Constructive methods for scheduling uniform loop nests A Darte, Y Robert IEEE transactions on Parallel and Distributed Systems 5 (8), 814-822, 1994 | 169 | 1994 |
| Programmatic iteration scheduling for parallel processors RS Schreiber, BR Rau, A Darte US Patent 6,438,747, 2002 | 133 | 2002 |
| Loop parallelization algorithms: From parallelism extraction to code generation P Boulet, A Darte, GA Silber, F Vivien Parallel Computing 24 (3-4), 421-444, 1998 | 133 | 1998 |
| Optimal fine and medium grain parallelism detection in polyhedral reduced dependence graphs A Darte, F Vivien International Journal of Parallel Programming 25 (6), 447-496, 1997 | 118 | 1997 |
| Regular partitioning for synthesizing fixed-size systolic arrays A Darte Integration 12 (3), 293-304, 1991 | 117 | 1991 |
| Linear scheduling is nearly optimal A Darte, L Khachiyan, Y Robert Parallel Processing Letters 1 (02), 73-81, 1991 | 115 | 1991 |
| (Pen)-ultimate tiling? P Boulet, A Darte, T Risset, Y Robert Integration 17 (1), 33-51, 1994 | 110 | 1994 |
| Combining retiming and scheduling techniques for loop parallelization and loop tiling A Darte, GA Silber, F Vivien Parallel Processing Letters 7 (04), 379-392, 1997 | 105 | 1997 |
| Mapping uniform loop nests onto distributed memory architectures A Darte, Y Robert Parallel Computing 20 (5), 679-710, 1994 | 101 | 1994 |
| Programmatic method for reducing cost of control in parallel processes A Darte, RS Schreiber US Patent 6,374,403, 2002 | 100 | 2002 |
| Affine-by-statement scheduling of uniform and affine loop nests over parametric domains A Darte, Y Robert Journal of Parallel and Distributed Computing 29 (1), 43-59, 1995 | 92 | 1995 |
| Register allocation: What does the NP-completeness proof of Chaitin et al. really prove? or revisiting register allocation: Why and how F Bouchez, A Darte, C Guillon, F Rastello International Workshop on Languages and Compilers for Parallel Computing …, 2006 | 89 | 2006 |
| Circuit retiming applied to decomposed software pipelining PY Calland, A Darte, Y Robert IEEE transactions on parallel and distributed systems 9 (1), 24-35, 1998 | 76 | 1998 |
| Revisiting out-of-SSA translation for correctness, code quality and efficiency B Boissinot, A Darte, F Rastello, BD de Dinechin, C Guillon 2009 International Symposium on Code Generation and Optimization, 114-125, 2009 | 71 | 2009 |
| On the complexity of register coalescing F Bouchez, A Darte, F Rastello International symposium on code generation and optimization (CGO'07), 102-114, 2007 | 59 | 2007 |
| Bee+ Cl@ k: An implementation of lattice-based array contraction in the source-to-source translator Rose C Alias, F Baray, A Darte ACM SIGPLAN Notices 42 (7), 73-82, 2007 | 53 | 2007 |
