| Co-Designing Accelerators and SoC Interfaces using gem5-Aladdin YS Shao, SL Xi, V Srinivasan, GY Wei, D Brooks International Symposium on Microarchitecture (MICRO), 2016 | 217 | 2016 |
| Quantifying sources of error in McPAT and potential impacts on architectural studies SL Xi, H Jacobson, P Bose, GY Wei, D Brooks 2015 IEEE 21st International symposium on high performance computer …, 2015 | 149 | 2015 |
| Beyond the Wall: Near-Data Processing for Databases SL Xi, O Babarinsa, M Athanassoulis, S Idreos Proceedings of the 11th International Workshop on Data Management on New …, 2015 | 108 | 2015 |
| A modular digital VLSI flow for high-productivity SoC design B Khailany, E Khmer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ... Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 76 | 2018 |
| SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads SL Xi, Y Yao, K Bhardwaj, P Whatmough, GY Wei, D Brooks ACM Transactions on Architecture and Code Optimization 17 (4), 2020 | 65 | 2020 |
| Mallacc: Accelerating Memory Allocation S Kanev, SL Xi, GY Wei, D Brooks Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2017 | 57 | 2017 |
| A 16nm 25mm2 SoC with a 54.5x Flexibility-Efficiency Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators PN Whatmough, SK Lee, M Donato, HC Hsueh, S Xi, U Gupta, ... 2019 Symposium on VLSI Circuits, C34-C35, 2019 | 40 | 2019 |
| Toward Cache-Friendly Hardware Accelerators YS Shao, S Xi, V Srinivasan, GY Wei, D Brooks Workshop on Sensors and Cloud Architectures, HPCA, 2015 | 37 | 2015 |
| Self-assembled resonance energy transfer keys for secure communication over classical channels V Nellore, S Xi, C Dwyer ACS nano 9 (12), 11840-11848, 2015 | 28 | 2015 |
| Understanding the critical path in power state transition latencies SL Xi, M Guevara, J Nelson, P Pensabene, BC Lee International Symposium on Low Power Electronics and Design (ISLPED), 317-322, 2013 | 14 | 2013 |
| automemcpy: A framework for automatic generation of fundamental memory operations G Chatelet, C Kennelly, SL Xi, O Sykora, C Courbet, D Li, B De Backer | 4 | 2021 |
| Methods and infrastructure in the era of accelerator-centric architectures B Reagen, YS Shao, SL Xi, GY Wei, D Brooks 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | | 2017 |
Gu-Yeon WeiRobert and Suzanne Case Professor of EE and CS, Harvard UniversityEmail verificata su eecs.harvard.edu
