Follow
Jose T. de Sousa
Jose T. de Sousa
INESC-ID / Tecnico University of Lisbon
Verified email at inesc-id.pt
Title
Cited by
Cited by
Year
Defect level evaluation in an IC design environment
JT De Sousa, FM Gonçalves, JP Teixeira, C Marzocca, F Corsi, ...
IEEE transactions on computer-aided design of integrated circuits and …, 1996
711996
Moving deep learning to the edge
MP Véstias, RP Duarte, JT de Sousa, HC Neto
Algorithms 13 (5), 125, 2020
622020
Network core access architecture
JT De Sousa, NCC Lourenco, NGDR Ribeiro, VMG Martins, RJS Martins
US Patent 8,019,832, 2011
522011
A SAT Solver using Reconfigurable Hardware and Virtual Logic
M Abramovici, J.T. de Sousa
SAT 2000, Highlights of Satisfiability Research in the Year 2000,, 377-402, 2001
522001
A SAT solver using reconfigurable hardware and virtual logic
M Abramovici, JT De Sousa
Journal of Automated Reasoning 24 (1), 5-36, 2000
522000
IC Defects-Based Testability Analysis
JJT Sousa, FM Gonçalves, ...
International Test Conference (ITC), 500-509, 1991
511991
A massively-parallel easily-scalable satisfiability solver using reconfigurable hardware
M Abramovici, JT de Sousa, D Saab
Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 684-690, 1999
481999
A Full Featured Configurable Accelerator for Object Detection with YOLO
D Pestana, PR Miranda, JD Lopes, RP Duarte, M Véstias, H C. Neto, ...
IEEE Access, 2021
442021
Virtual logic system for solving satisfiability problems using reconfigurable hardware
M Abramovici, JT De Sousa
US Patent 6,442,732, 2002
442002
A configurable hardware/software approach to SAT solving
JT de Sousa, JM Da Silva, M Abramovici
The 9th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2001
432001
Parallel backtracing for satisfiability on reconfigurable hardware
M Abramovici, JT De Sousa, DG Saab
US Patent 6,292,916, 2001
342001
Reducing the complexity of defect level modeling using the clustering effect
JT de Sousa, VD Agrawal
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2000
342000
A 1.7-mW -92-dBm Sensitivity Low-IF Receiver in 0.13-μm CMOS for Bluetooth LE Applications.
M Pereira, J T. de Sousa, J Freire, J Vaz
IEEE Transactions on Microwave Theory and Techniques, 1-15, 2018
33*2018
Parallel Dot-Products for Deep Learning on FPGA
M Véstias, R Duarte, JT de Sousa, H Neto
27th Int. Conference on Field Programmable Logic and Applications, 2017
332017
Physical DFT for High Coverage of Realistic Faults
M Saraiva, P Casimiro, M Santos, JT Sousa, FM Gonçalves, I Teixeira, ...
Int. Test Conference (ITC), 642-651, 1992
291992
Fault Modeling and Defect Level Projections in Digital ICs
JT Sousa, FM Gonçalves, JP Teixeira, TW Williams
European Design and Test Conference (ED&TC), 436-442, 1994
241994
A fast and scalable architecture to run convolutional neural networks in low density FPGAs
MP Véstias, RP Duarte, JT de Sousa, HC Neto
Microprocessors and Microsystems 77, 103136, 2020
222020
Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs
HN Mário P. Véstias, Rui Policarpo Duarte, José T. de Sousa
28th International Conference on Field Programmable Logic and Applications (FPL), 2018
202018
Fault simulation using partially reconfigurable hardware
A Parreira, JP Teixeira, A Pantelimon, MB Santos, JT de Sousa
Field Programmable Logic and Application: 13th International Conference, FPL …, 2003
202003
On implementing a configware/software SAT solver
NA Reis, JT de Sousa
Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom …, 2002
202002
The system can't perform the operation now. Try again later.
Articles 1–20