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Christopher Pulte
Christopher Pulte
Verified email at cam.ac.uk - Homepage
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Year
Modelling the ARMv8 architecture, operationally: Concurrency and ISA
S Flur, KE Gray, C Pulte, S Sarkar, A Sezgin, L Maranget, W Deacon, ...
Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of …, 2016
1632016
Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8
C Pulte, S Flur, W Deacon, J French, S Sarkar, P Sewell
Proceedings of the ACM on Programming Languages 2 (POPL), 1-29, 2017
1352017
ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS
A Armstrong, T Bauereiss, B Campbell, A Reid, KE Gray, R Norton-Wright, ...
Association for Computing Machinery (ACM), 2019
812019
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors
KE Gray, G Kerneis, D Mulligan, C Pulte, S Sarkar, P Sewell
Proceedings of the 48th International Symposium on Microarchitecture, 635-646, 2015
442015
Mixed-size concurrency: ARM, Power, C/C++ 11, and SC
S Flur, S Sarkar, C Pulte, K Nienhuis, L Maranget, KE Gray, A Sezgin, ...
ACM SIGPLAN Notices 52 (1), 429-442, 2017
402017
Promising-ARM/RISC-V: a simpler and faster operational concurrency model
C Pulte, J Pichon-Pharabod, J Kang, SH Lee, CK Hur
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language …, 2019
312019
Repairing and mechanising the JavaScript relaxed memory model
C Watt, C Pulte, A Podkopaev, G Barbier, S Dolan, S Flur, ...
Proceedings of the 41st ACM SIGPLAN Conference on Programming Language …, 2020
152020
ARMv8-A system semantics: instruction fetch in relaxed architectures
B Simner, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ...
European Symposium on Programming, 626-655, 2020
102020
Detailed models of instruction set architectures: From pseudocode to formal semantics
A Armstrong, T Bauereiss, B Campbell, S Flur, KE Gray, P Mundkur, ...
Proceedings of the 25th Automated Reasoning Workshop: Bridging the Gap …, 2018
82018
The semantics of multicopy atomic ARMv8 and RISC-V
C Pulte
University of Cambridge, 2019
72019
Isla: Integrating full-scale ISA semantics and axiomatic concurrency models
A Armstrong, B Campbell, B Simner, C Pulte, P Sewell
International Conference on Computer Aided Verification, 303-316, 2021
52021
The sail instruction-set semantics specification language
KE Gray, P Sewell, C Pulte, S Flur, R Norton-Wright
Technical report published by Cambridge University, 2017
52017
Relaxed virtual memory in Armv8-A
B Simner, A Armstrong, J Pichon-Pharabod, C Pulte, R Grisenthwaite, ...
European Symposium on Programming, 143-173, 2022
32022
Sail
A Armstrong, T Bauereiss, B Campbell, S Gray, G Kerneis, ...
32019
The Sail instruction-set semantics specification language
A Armstrong, T Bauereiss, B Campbell, KE Gray, R Norton-Wright, C Pulte, ...
22021
Isla: integrating full-scale ISA semantics and axiomatic concurrency models (extended version)
A Armstrong, B Campbell, B Simner, C Pulte, P Sewell
Extended version of a paper in Proceedings of CAV, 2021
12021
Relaxed virtual memory in Armv8-A (extended version)
B Simner, A Armstrong, J Pichon-Pharabod, C Pulte, R Grisenthwaite, ...
arXiv preprint arXiv:2203.00642, 2022
2022
Promising-ARM/RISC-V: A simpler and faster operational concurrency model
CK Hur, SH Lee, J Kang, J Pichon-Pharabod, C Pulte
Association for Computing Machinery, 2019
2019
Research data supporting “Mixed-size Concurrency: ARM, POWER, C/C++ 11, and SC”
S Flur, S Sarkar, C Pulte, K Nienhuis, L Maranget, KE Gray, A Sezgin, ...
University of Cambridge, 2016
2016
An Axiomatic Semantics for Instruction Fetching
B Simner, S Flur, C Pulte, A Armstrong, J Pichon-Pharabod, L Maranget, ...
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Articles 1–20