| Compact models and performance investigations for subthreshold interconnects R Dhiman, R Chandel Springer India, 2015 | 16 | 2015 |
| High-performance current mode receiver design for on-chip VLSI interconnects Y Agrawal, R Chandel, R Dhiman Intelligent Computing and Applications: Proceedings of the International …, 2015 | 16 | 2015 |
| Proposal and analysis of mixed CNT bundle for sub-threshold interconnects A Singh, R Dhiman IEEE Transactions on Nanotechnology 18, 584-588, 2019 | 14 | 2019 |
| SiGe/Si hetero nanotube JLFET for improved performance: proposal and investigation A Thakur, R Dhiman Electronics Letters 55 (25), 1359-1361, 2019 | 12 | 2019 |
| Variability analysis of stochastic parameters on the electrical performance of on-chip current-mode interconnect system Y Agrawal, R Chandel, R Dhiman IETE Journal of Research 63 (2), 268-280, 2017 | 12 | 2017 |
| Dynamic crosstalk analysis in coupled interconnects for ultra-low power applications R Dhiman, R Chandel Circuits, Systems, and Signal Processing 34, 21-40, 2015 | 12 | 2015 |
| Design and analysis of efficient multilevel receiver for current mode interconnect system Y Agrawal, R Chandel, R Dhiman 2014 IEEE Students' Conference on Electrical, Electronics and Computer …, 2014 | 12 | 2014 |
| Delay analysis of buffer inserted sub-threshold interconnects R Dhiman, R Chandel Analog Integrated Circuits and Signal Processing 90, 435-445, 2017 | 11 | 2017 |
| Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects A Singh, R Chandel, R Dhiman Integration 80, 29-40, 2021 | 9 | 2021 |
| Impacts of core gate thickness and Ge content variation on the performance of Si1−xGex source/drain Si–nanotube JLFET A Thakur, R Dhiman Journal of Computational Electronics 20, 237-247, 2021 | 8 | 2021 |
| Design and performance analysis of SiGe hetero nanotube junctionless FET A Thakur, R Dhiman TENCON 2019-2019 IEEE Region 10 Conference (TENCON), 2424-2427, 2019 | 7 | 2019 |
| Crosstalk analysis of CMOS buffer driven interconnects for ultra-low power applications R Dhiman, R Chandel Journal of Computational Electronics 13, 360-369, 2014 | 7 | 2014 |
| A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement A Thakur, R Dhiman Microelectronics Journal 126, 105501, 2022 | 6 | 2022 |
| Proposal and analysis of carbon nanotube based differential multibit through glass vias A Kumar, R Chandel, R Dhiman Microelectronics Journal 126, 105500, 2022 | 5 | 2022 |
| Modeling of mixed CNT bundle for sub-threshold interconnects A Singh, R Dhiman, R Chandel 2018 IEEE Electrical Design of Advanced Packaging and Systems Symposium …, 2018 | 5 | 2018 |
| A 60 db bulk-driven rail-to-rail input/output OTA A Shrivastava, AP Gangwar, R Kumar, R Dhiman 2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016 | 5 | 2016 |
| Performance analysis of top-contact MLGNR based interconnects R Kumar, R Dhiman, R Chandel 2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016 | 4 | 2016 |
| Design challenges in subthreshold interconnect circuits R Dhiman, R Chandel, R Dhiman, R Chandel Compact Models and Performance Investigations for Subthreshold Interconnects …, 2015 | 4 | 2015 |
| Sub-threshold delay and power analysis of complementary metal-oxide semiconductor buffer driven interconnect load for ultra low power applications R Dhiman, R Chandel Journal of Low Power Electronics 8 (1), 39-46, 2012 | 4 | 2012 |
| Modeling and analysis of Cu-CNT composite through glass vias in 3D ICs A Kumar, R Dhiman 2021 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS), 1-3, 2021 | 3 | 2021 |
