Srinivasan Murali
Srinivasan Murali
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TitleCited byYear
Bandwidth-constrained mapping of cores onto NoC architectures
S Murali, G De Micheli
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
7812004
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
D Bertozzi, A Jalabert, S Murali, R Tamhankar, S Stergiou, L Benini, ...
IEEE transactions on parallel and distributed systems 16 (2), 113-129, 2005
6682005
Analysis of error recovery schemes for networks on chips
S Murali, T Theocharides, N Vijaykrishnan, MJ Irwin, L Benini, ...
IEEE Design & Test of Computers 22 (5), 434-442, 2005
3662005
SUNMAP: a tool for automatic topology selection and generation for NoCs
S Murali, G De Micheli, G De Micheli, G De Micheli
Proceedings of the 41st annual Design Automation Conference, 914-919, 2004
3662004
xpipesCompiler: A tool for instantiating application-specific Networks on Chip
A Jalabert, S Murali, L Benini, G De Micheli
Design, Automation, and Test in Europe, 157-171, 2008
3452008
Networks on chips
L Benini, G De Micheli, D Bertozzi, I Cidon, K Goossens, K Kim, K Lee, ...
Elsevier, 2006
2922006
Designing application-specific networks on chips with floorplan information
S Murali, P Meloni, F Angiolini, D Atienza, S Carta, L Benini, G De Micheli, ...
2006 IEEE/ACM International Conference on Computer Aided Design, 355-362, 2006
2282006
A methodology for mapping multiple use-cases onto networks on chips
S Murali, M Coenen, A Radulescu, K Goossens, G De Micheli
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
1942006
Network-on-chip design and synthesis outlook
D Atienza, F Angiolini, S Murali, A Pullini, L Benini, G De Micheli
Integration 41 (3), 340-359, 2008
1572008
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
S Murali, A Mutapcic, D Atienza, R Gupta, S Boyd, G De Micheli
Proceedings of the 5th IEEE/ACM international conference on Hardware …, 2007
1552007
Sunfloor 3d: A tool for networks on chip topology synthesis for 3-d systems on chips
C Seiculescu, S Murali, L Benini, G De Micheli
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
1412010
Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees
S Murali, S Murali, L Benini, G De Micheli, G De Micheli, G De Micheli
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
1402005
Temperature control of high-performance multi-core platforms using convex optimization
S Murali, A Mutapcic, D Atienza, R Gupta, S Boyd, L Benini, G De Micheli
Proceedings of the conference on Design, automation and test in Europe, 110-115, 2008
1162008
Synthesis of networks on chips for 3D systems on chips
S Murali, C Seiculescu, L Benini, G De Micheli
2009 Asia and South Pacific Design Automation Conference, 242-247, 2009
1122009
Mapping and configuration methods for multi-use-case networks on chips
S Murali, M Coenen, A Radulescu, K Goossens, G De Micheli
Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006
1112006
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
M Coenen, S Murali, S Murali, A Ruadulescu, K Goossens, G De Micheli, ...
Proceedings of the 4th international conference on Hardware/software …, 2006
942006
Bringing NoCs to 65 nm
A Pullini, F Angiolini, S Murali, D Atienza, G De Micheli, L Benini
IEEE Micro 27 (5), 75-85, 2007
922007
A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip
S Murali, D Atienza, L Benini, G De Micheli
2006 43rd ACM/IEEE Design Automation Conference, 845-848, 2006
902006
Method to design network-on-chip (NOC)-based communication systems
S Murali, L Benini, G De Micheli
US Patent 8,042,087, 2011
872011
An application-specific design methodology for STbus crossbar generation
S Murali, GD Micheli
Proceedings of the conference on Design, Automation and Test in Europe …, 2005
872005
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Articles 1–20