| Soft error interception latch: Double node charge sharing SEU tolerant design K Katsarou, Y Tsiatouhas Electronics Letters 51 (4), 330-332, 2015 | 119 | 2015 |
| Double node charge sharing SEU tolerant latch design K Katsarou, Y Tsiatouhas 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 122-127, 2014 | 72 | 2014 |
| New high-speed multioutput carry look-ahead adders C Efstathiou, Z Owda, Y Tsiatouhas IEEE Transactions on Circuits and Systems II: Express Briefs 60 (10), 667-671, 2013 | 55 | 2013 |
| Octupole Vibration in Superdeformed T Lauritsen, RVF Janssens, MP Carpenter, P Fallon, B Herskind, ... Physical review letters 89 (28), 282501, 2002 | 51 | 2002 |
| Comparative study of different current mode sense amplifiers in submicron CMOS technology A Chrisanthopoulos, Y Moisiadis, Y Tsiatouhas, A Arapoyanni IEE Proceedings-Circuits, Devices and Systems 149 (3), 154-158, 2002 | 47 | 2002 |
| Timing error tolerance in nanometer ICs S Valadimas, Y Tsiatouhas, A Arapoyanni 2010 IEEE 16th International On-Line Testing Symposium, 283-288, 2010 | 31 | 2010 |
| A built-in-test circuit for RF differential low noise amplifiers LE Dermentzoglou, A Arapoyanni, Y Tsiatouhas IEEE Transactions on Circuits and Systems I: Regular Papers 57 (7), 1549-1558, 2010 | 30 | 2010 |
| A circuit for concurrent detection of soft and timing errors in digital CMOS ICs S Matakias, Y Tsiatouhas, A Arapoyanni, T Haniotakis Journal of Electronic Testing 20, 523-531, 2004 | 28 | 2004 |
| The time dilation technique for timing error tolerance S Valadimas, A Floros, Y Tsiatouhas, A Arapoyanni, X Kavousianos IEEE Transactions on Computers 63 (5), 1277-1286, 2012 | 24 | 2012 |
| New memory sense amplifier designs in CMOS technology Y Tsiatouhas, A Chrisanthopoulos, G Kamoulakos, T Haniotakis ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and …, 2000 | 24 | 2000 |
| Static power reduction using variation-tolerant and reconfigurable multi-mode power switches Z Zhang, X Kavousianos, K Chakrabarty, Y Tsiatouhas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (1), 13-26, 2013 | 23 | 2013 |
| Fast deployment of alternate analog test using Bayesian model fusion J Liaperdos, HG Stratigopoulos, L Abdallah, Y Tsiatouhas, A Arapoyanni, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 21 | 2015 |
| Low power scan by partitioning and scan hold E Arvaniti, Y Tsiatouhas 2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012 | 21 | 2012 |
| Cost and power efficient timing error tolerance in flip-flop based microprocessor cores S Valadimas, Y Tsiatouhas, A Arapoyanni 2012 17th IEEE European Test Symposium (ETS), 1-6, 2012 | 20 | 2012 |
| A robust and reconfigurable multi-mode power gating architecture Z Zhang, X Kavousianos, K Chakrabarty, Y Tsiatouhas 2011 24th Internatioal Conference on VLSI Design, 280-285, 2011 | 20 | 2011 |
| A stress-relaxed negative voltage-level converter YE Tsiatouhas IEEE Transactions on Circuits and Systems II: Express Briefs 54 (3), 282-286, 2007 | 19 | 2007 |
| A design technique for energy reduction in NORA CMOS logic K Limniotis, Y Tsiatouhas, T Haniotakis, A Arapoyanni IEEE Transactions on Circuits and Systems I: Regular Papers 53 (12), 2647-2655, 2006 | 19 | 2006 |
| A hierarchical architecture for concurrent soft error detection based on current sensing Y Tsiatouhas, A Arapoyanni, D Nikolos, T Haniotakis Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW …, 2002 | 19 | 2002 |
| Timing error tolerance in small core designs for SoC applications S Valadimas, Y Tsiatouhas, A Arapoyanni IEEE Transactions on Computers 65 (2), 654-663, 2015 | 18 | 2015 |
| The time dilation scan architecture for timing error detection and correction A Floros, Y Tsiatouhas, X Kavousianos IFIP/IEEE International Conference on Very Large Scale Integration, 569-574, 2008 | 17 | 2008 |
John LiaperdosAssistant Professor of Electronics, Department of Digital Systems, University of the PeloponneseVerified email at uop.gr
