| An opencl™ deep learning accelerator on arria 10 U Aydonat, S O'Connell, D Capalija, AC Ling, GR Chiu Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 345 | 2017 |
| A high-performance overlay architecture for pipelined execution of data flow graphs D Capalija, TS Abdelrahman 2013 23rd International Conference on Field programmable Logic and …, 2013 | 109 | 2013 |
| A multithreaded soft processor for SoPC area reduction B Fort, D Capalija, ZG Vranesic, SD Brown 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing …, 2006 | 88 | 2006 |
| Method and apparatus for performing different types of convolution operations with the same processing elements M Lele, D Capalija, AC Ling US Patent 11,074,492, 2021 | 43 | 2021 |
| In-package domain-specific ASICs for intel® stratix® 10 FPGAs: A case study of accelerating deep learning using tensortile ASIC E Nurvitadhi, J Cook, A Mishra, D Marr, K Nealis, P Colangelo, A Ling, ... 2018 28th International Conference on Field Programmable Logic and …, 2018 | 39 | 2018 |
| Towards synthesis-free JIT compilation to commodity FPGAs D Capalija, TS Abdelrahman 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom …, 2011 | 35 | 2011 |
| Tile-based bottom-up compilation of custom mesh-of-functional-units FPGA overlays D Capalija, TS Abdelrahman 2014 24th International Conference on Field Programmable Logic and …, 2014 | 28 | 2014 |
| Microarchitecture of a coarse-grain out-of-order superscalar processor D Capalija, TS Abdelrahman IEEE Transactions on Parallel and Distributed Systems 24 (2), 392-405, 2012 | 20 | 2012 |
| Customizable FPGA OpenCL matrix multiply design template for deep neural networks J Yinger, E Nurvitadhi, D Capalija, A Ling, D Marr, S Krishnan, D Moss, ... 2017 International Conference on Field Programmable Technology (ICFPT), 259-262, 2017 | 17 | 2017 |
| Coopetition mechanisms for service-oriented distributed systems A Milanović, S Srbljić, D Skrobo, D Čapalija, S Rešković The 3rd International Conference on Computing, Communication and Control …, 2005 | 17 | 2005 |
| Flexibility: FPGAs and CAD in deep learning acceleration GR Chiu, AC Ling, D Capalija, A Bitar, MS Abdelfattah Proceedings of the 2018 International Symposium on Physical Design, 34-41, 2018 | 16 | 2018 |
| The MLCA: a solution paradigm for parallel programmable SoCs T Abdelrahman, A Abdelkhalek, U Aydonat, D Capalija, D Han, ... IEEE North-East Workshop on Circuits and Systems (NEWCAS), 253-253, 2006 | 14 | 2006 |
| Compute substrate for Software 2.0 J Vasiljevic, L Bajic, D Capalija, S Sokorac, D Ignjatovic, L Bajic, ... IEEE micro 41 (2), 50-55, 2021 | 13 | 2021 |
| A coarse-grain fpga overlay for executing data flow graphs D Capalija, T Abdelrahman The Second Workshop on the Intersections of Computer Architecture and …, 2012 | 11 | 2012 |
| Creating High Performance Applications with Intel's FPGA OpenCL™ SDK AC Ling, U Aydonat, S O'Connell, D Capalija, GR Chiu Proceedings of the 5th International Workshop on OpenCL, 1-1, 2017 | 9 | 2017 |
| An architecture for exploiting coarse-grain parallelism on FPGAs D Capalija, TS Abdelrahman 2009 International Conference on Field-Programmable Technology, 285-291, 2009 | 9 | 2009 |
| Dot product based processing elements AC Ling, D Capalija, TS Czajkowski, AMH Miriste US Patent 10,049,082, 2018 | 6 | 2018 |
| Microarchitecture and FPGA implementation of the multi-level computing architecture D Capalija University of Toronto, 2008 | 4 | 2008 |
| Objava-pretplata mehanizmi za ostvarivanje mreža zasnovanih na sadržaju D Čapalija diplomski rad, Fakultet elektrotehnike i računarstva, Sveučilište u Zagrebu …, 2005 | 4 | 2005 |
| Processor cores using packet identifiers for routing and computation D Capalija, L Bajic, J Vasiljevic US Patent 11,269,628, 2022 | 2 | 2022 |
Ljubisa BajicCEO, TenstorrentVerified email at tenstorrent.com
