Arash Saifhashemi
Arash Saifhashemi
Research Scientist, Intel Labs
Verified email at intel.com
TitleCited byYear
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction
A Saifhashemi, H Pedram
Proceedings 2003. Design Automation Conference (IEEE Cat. No. 03CH37451 …, 2003
582003
Power aware asynchronous circuits
K Shiring, PA Beerel, A Lines, A Saifhashemi
US Patent 8,086,975, 2011
272011
Power aware asynchronous circuits
K Shiring, PA Beerel, A Lines, A Saifhashemi
US Patent 8,086,975, 2011
272011
Power aware asynchronous circuits
K Shiring, PA Beerel, A Lines, A Saifhashemi
US Patent 8,086,975, 2011
272011
High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog.
A Saifhashemi, PA Beerel
CPA, 275-288, 2005
152005
SystemVerilogCSP: Modeling Digital Asynchronous Circuits Using SystemVerilog Interfaces.
A Saifhashemi, PA Beerel
CPA, 287-302, 2011
112011
Performance and area optimization of a bundled-data intel processor through resynthesis
A Saifhashemi, D Hand, PA Beerel, W Koven, H Wang
2014 20th IEEE International Symposium on Asynchronous Circuits and Systems …, 2014
72014
MILO: Personal robot platform
B Salemi, J Reis, A Saifhashemi, F Nikgohar
2005 IEEE/RSJ International Conference on Intelligent Robots and Systems …, 2005
72005
Power optimization of asynchronous pipelines using conditioning and reconditioning based on a three-valued logic model
A Saifhashemi
University of Southern California, 2012
62012
Notes on pulse signaling
J Ebergen, S Furber, A Saifhashemi
Proceedings of the 13th IEEE International Symposium on Asynchronous …, 2007
62007
PERSIA: An Asynchronous Synthesis Tool Based on Alain Martin's Method
A Seifhashemi, M Naderi, K Saleh, M Salehi, H Pedram
CAD Tutorial, 9th IEEE International Symposium on Asynchronous Systems …, 2003
62003
Observability conditions and automatic operand-isolation in high-throughput asynchronous pipelines
A Saifhashemi, PA Beerel
International Workshop on Power and Timing Modeling, Optimization and …, 2012
52012
Verilog HDL, a Replacement for CSP
A Seifhashemi, H Pedram
3rd Asynchronous Circuit Design Workshop-ACiD-WG, Heraklion, Greece, 2003
42003
Logical equivalence checking of asynchronous circuits using commercial tools
A Saifhashemi, HH Huang, P Bhalerao, PA Beerel
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
22015
Reconditioning: Automatic power optimization of QDI circuits
A Saifhashemi, HH Huang, PA Beerel
2014 20th IEEE International Symposium on Asynchronous Circuits and Systems …, 2014
22014
Reconditioning: a framework for automatic power optimization of QDI circuits
A Saifhashemi, HH Huang, PA Beerel
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
12016
Using Standard HDLs and CAD Tools for the Design and Simulation of Asynchronous Circuits
A Saifhashemi, M Naderi, H Pedram, A Farhoodfar
THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING 1 (4), 1-10, 2003
12003
Symposium Committee
W Pages
2016
Notes On Pulse Signaling
A Chow, N Nissar, A Saifhashemi, S Furber, J Ebergen
13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007
2007
ASYNC 2018
J Bainbridge, P Beerel, E Beigne, D Bertozzi, K Boahen, E Brunvand, ...
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