Marco Elver
TitleCited byYear
TSO-CC: Consistency directed cache coherence for TSO
M Elver, V Nagarajan
2014 IEEE 20th International Symposium on High Performance Computer …, 2014
An automated and reproducible workflow for running and analyzing neural simulations using Lancet and IPython Notebook
JLR Stevens, M Elver, JA Bednar
Frontiers in neuroinformatics 7, 44, 2013
McVerSi: A test generation framework for fast memory consistency verification in simulation
M Elver, V Nagarajan
2016 IEEE International Symposium on High Performance Computer Architecture …, 2016
C3D: Mitigating the NUMA bottleneck via coherent DRAM caches
CC Huang, R Kumar, M Elver, B Grot, V Nagarajan
2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016
RC3: Consistency directed cache coherence for x86-64 with RC extensions
M Elver, V Nagarajan
2015 International Conference on Parallel Architecture and Compilation (PACT …, 2015
Verification of a lazy cache coherence protocol against a weak memory model
CJ Banks, M Elver, R Hoffmann, S Sarkar, P Jackson, V Nagarajan
Proceedings of the 17th Conference on Formal Methods in Computer-Aided …, 2017
TSO-CC specification
M Elver
Fast RMWs for TSO: Semantics and implementation
B Rajaram, V Nagarajan, S Sarkar, M Elver
ACM SIGPLAN Notices 48 (6), 61-72, 2013
VerC3: A library for explicit state synthesis of concurrent systems
M Elver, CJ Banks, P Jackson, V Nagarajan
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
Memory consistency directed cache coherence protocols for scalable multiprocessors
MI Elver
The University of Edinburgh, 2016
Optimising Topographica for Shared Memory Architectures
M Elver
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Articles 1–11