| Design issues and considerations for low-cost 3-D TSV IC technology G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ... IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010 | 388 | 2010 |
| Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k/metal gate CMOS performance A Mercha, G Van der Plas, V Moroz, I De Wolf, P Asimakopoulos, N Minas, ... 2010 International Electron Devices Meeting, 2.2. 1-2.2. 4, 2010 | 140 | 2010 |
| On-chip testing using time-to-digital conversion N Minas, EJ Marinissen US Patent 8,680,874, 2014 | 37 | 2014 |
| Impact of thinning and through silicon via proximity on high-k/metal gate first CMOS performance A Mercha, A Redolfi, M Stucchi, N Minas, J Van Olmen, S Thangaraju, ... 2010 Symposium on VLSI Technology, 109-110, 2010 | 27 | 2010 |
| A high resolution flash time-to-digital converter taking into account process variability N Minas, D Kinniment, K Heron, G Russell 13th IEEE International Symposium on Asynchronous Circuits and Systems …, 2007 | 24 | 2007 |
| On-chip testing using time-to-digital conversion N Minas, EJ Marinissen | 15 | 2012 |
| Test structures for characterization of thermal-mechanical stress in 3D stacked IC for analog design N Minas, G Van der Plas, H Oprins, Y Yang, C Okoro, A Mercha, ... 2010 International Conference on Microelectronic Test Structures (ICMTS …, 2010 | 15 | 2010 |
| 3D integration: Circuit design, test, and reliability challenges N Minas, I De Wolf, EJ Marinissen, M Stucchi, H Oprins, A Mercha, ... 2010 IEEE 16th International On-Line Testing Symposium (IOLTS 2010), 217-217, 2010 | 10 | 2010 |
| An efficient array structure to characterize the impact of through silicon vias on FET devices D Perry, J Cho, S Domae, P Asimakopoulos, A Yakovlev, P Marchal, ... 2011 IEEE ICMTS International Conference on Microelectronic Test Structures …, 2011 | 9 | 2011 |
| Fpga implementation of an asynchronous processor with both online and offline testing capabilities N Minas, M Marshall, G Russell, A Yakovlev 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems …, 2008 | 7 | 2008 |
| Design of test structures for the characterization of thermal–mechanical stress in 3D-stacked IC N Minas, G Van der Plas, H Oprins, Y Yang, C Okoro, A Mercha, ... IEEE transactions on semiconductor manufacturing 25 (3), 365-371, 2012 | 5 | 2012 |
| In-tier diagnosis of power domains in 3D TSV ICs Y Araga, M Nagata, G Van der Plas, J Kim, N Minas, P Marchal, Y Travaly, ... 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE …, 2012 | 4 | 2012 |
| High resolution flash time-to-digital converter with sub-picosecond measurement capabilities N Minas, D Kinniment, G Russell, A Yakovlev 2008 International Symposium on System-on-Chip, 1-4, 2008 | 3 | 2008 |
| NoC communication strategies using time-to-digital conversion C D'Alessandro, N Minas, K Heron, D Kinniment, A Yakovlev First International Symposium on Networks-on-Chip (NOCS'07), 65-74, 2007 | 3 | 2007 |
| “Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k/metal gate cmos performance,” IEEE International Electron Devices … A Mercha, G Van der Plas, V Moroz, I De Wolf, P Asimakopoulos, N Minas, ... | 2 | 2010 |
| Intra/Inter Tier Substrate Noise Measurements in 3D ICs Y Takagi, Y Araga, M Nagata, GV Plas, J Kim, N Minas, P Marchal, ... IEICE Technical Report; IEICE Tech. Rep. 112 (170), 49-54, 2012 | | 2012 |
| On-Chip Architecture for Time Interval Measurements with Sub-Picosecond Resolution N Minas University of Newcastle Upon Tyne, 2009 | | 2009 |
| PROCEEDINGS-NOCS 2007: FIRST INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP C D'Alessandro, N Minas, K Heron, D Kinniment, A Yakovlev | | 2007 |
| NOCS 2010 R Abdel-Khalek, N Agarwal, K Aisopos, A Amory, P Asimakopoulos, ... | | |
a yakovlevNewcastle UniversityVerified email at newcastle.ac.uk
