Aiman El-Maleh

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Sadiq M. SaitKing Fahd University of Petroleum & MineralsVerified email at kfupm.edu.sa
Janusz RajskiVice President of Engineering, SiemensVerified email at mentor.com
Ahmad Tariq SheikhPostdoctoral Fellow, King Abdullah University of Science and Technology (KAUST)Verified email at kaust.edu.sa
Wojciech. MalyCMUVerified email at ece.cmu.edu
Muhmmad ElrabaaProfessor, Computer Engneering Department, King Fahd University for Petroleum and MineralsVerified email at kfupm.edu.sa
Ahmad ShawahnaAssistant Professor, Department of Electrical and Computer Engineering, Birzeit UniversityVerified email at birzeit.edu
Bashir M. Al-HashimiProfessor of Computer Engineering, King’s College LondonVerified email at kcl.ac.uk
Esam KhanUmm Al-Qura University - The Custodian of the Two Holy Mosques Institute for Hajj & Umrah ResearchVerified email at uqu.edu.sa
Habib YoussefProfessor of Computer Science, University of Sousse, TunisiaVerified email at fsm.rnu.tn
Feras Chikh OughaliResearch Engineer, King Fahd University of Petroleum & MineralsVerified email at kfupm.edu.sa
S KhursheedLecturer (Assistant Professor), University of Liverpool, UKVerified email at liv.ac.uk
Faisal KhanIntel CorporationVerified email at intel.com
Dr. Mustafa Imran AliaiMotive KftVerified email at aimotive.com
Mohammad AlshayebProfessor of Software Engineering, King Fahd University of Petroleum and MineralsVerified email at kfupm.edu.sa
Amran Al-AghbariPhD in Computer Science & EngineeringVerified email at kfupm.edu.sa
Ayman HroubDepartment of Electrical and Computer Engineering at Birzeit UniversityVerified email at birzeit.edu
Abdelhafid BouhraouaAssistant Professor Higher Colleges of TechnologyVerified email at hct.ac.ae
Vijay BhargavaElectrical and Computer Engineering, University of British ColumbiaVerified email at ece.ubc.ca
Dr. Saif alZahirPhDVerified email at encs.concordia.ca

Aiman El-Maleh

Professor of Computer Engineering, King Fahd University of Petroleum & Minerals

Verified email at kfupm.edu.sa - Homepage

Logic Synthesis VLSI Testing Fault Tolerance FPGAs Deep Learning


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FPGA-based accelerators of deep learning networks for learning and classification: A review A Shawahna, SM Sait, A El-Maleh ieee Access 7, 7823-7859, 2018	526	2018
Transistor-Level Defect Tolerant Digital System Design at the Nanoscale AH El-Maleh, A Al-Yamani, BM Al-Hashimi Research Proposal Submitted to Internal Track Research Grant Programs, 2007	246	2007
Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression AH El-Maleh, RH Al-Abaji 9th international conference on electronics, circuits and systems 2, 449-452, 2002	129	2002
A fault tolerance technique for combinational circuits based on selective-transistor redundancy AT Sheikh, AH El-Maleh, MES Elrabaa, SM Sait IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 224-237, 2016	128	2016
Test data compression for system-on-a-chip using extended frequency-directed run-length code AH El-Maleh IET Computers & Digital Techniques 2 (3), 155-163, 2008	101	2008
An efficient test relaxation technique for combinational & full-scan sequential circuits A El-Maleh, A Al-Suwaiyan Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 53-59, 2002	93	2002
Complexity of sequential ATPG TE Marchok, A El-Maleh, W Maly, J Rajski Proceedings the European Design and Test Conference. ED&TC 1995, 252-261, 1995	88	1995
Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits AH El-Maleh, AT Sheikh, SM Sait Applied soft computing 13 (12), 4832-4840, 2013	85	2013
A geometric-primitives-based compression scheme for testing systems-on-a-chip A El-Maleh, S Al Zahir, E Khan Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 54-59, 2001	83	2001
Defect-tolerant N2-transistor structure for reliable nanoelectronic designs AH El-Maleh, BM Al-Hashimi, A Melouki, F Khan IET computers & digital techniques 3 (6), 570-580, 2009	67	2009
Cuckoo search based resource optimization of datacenters SM Sait, A Bala, AH El-Maleh Applied Intelligence 44, 489-506, 2016	64	2016
Test vector decomposition-based static compaction algorithms for combinational circuits AH El-Maleh, YE Osais ACM Transactions on Design Automation of Electronic Systems (TODAES) 8 (4 …, 2003	61	2003
Efficient test compression technique based on block merging AH El-Maleh IET Computers & Digital Techniques 2 (5), 327-335, 2008	58	2008
Simulation-based method for synthesizing soft error tolerant combinational circuits AH El-Maleh, KAK Daud IEEE Transactions on Reliability 64 (3), 935-948, 2015	52	2015
An efficient test relaxation technique for synchronous sequential circuits A El-Maleh, K Al-Utaibi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004	52	2004
Finite state machine state assignment for area and power minimization A El-Maleh, SM Sait, FN Khan 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp., 2006	48	2006
A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits AH El-Maleh, FC Oughali Microelectronics Reliability 54 (1), 316-326, 2014	44	2014
Behavior and testability preservation under the retiming transformation A El-Maleh, TE Marchok, J Rajski, W Maly IEEE transactions on computer-aided design of integrated circuits and …, 1997	38	1997
A complexity analysis of sequential ATPG TE Marchok, A El-Maleh, W Maly, J Rajski IEEE transactions on computer-aided design of integrated circuits and …, 1996	37	1996
On test set preservation of retimed circuits A El-Maleh, T Marchok, J Rajski, W Maly Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 176-182, 1995	33	1995

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