| Methods and apparatus for dual-use coprocessing/debug interface E Barry US Patent App. 09/792,819, 2001 | 170* | 2001 |
| Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor GG Pechanek, JG Revilla, EF Barry US Patent 6,173,389, 2001 | 150 | 2001 |
| Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor JG Revilla, EF Barry, PR Marchand, GG Pechanek US Patent 6,216,223, 2001 | 127 | 2001 |
| Methods and apparatus for scalable instruction set architecture with dynamic compact instructions GG Pechanek, EF Barry, JG Revilla, LD Larsen US Patent 6,101,592, 2000 | 114* | 2000 |
| Method and apparatus for manifold array processing GG Pechanek, NP Pitsianis, EF Barry, TL Drabenstott US Patent 6,167,502, 2000 | 111 | 2000 |
| Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution TL Drabenstott, GG Pechanek, EF Barry, CW Kurak Jr US Patent 6,366,999, 2002 | 108 | 2002 |
| Method and apparatus for improving object selection on a computer display by providing cursor control with a sticky property EF Barry US Patent 5,786,805, 1998 | 96 | 1998 |
| Another look at the behaviors of novice programmers JB Fenwick Jr, C Norris, FE Barry, J Rountree, CJ Spicer, SD Cheek ACM SIGCSE Bulletin 41 (1), 296-300, 2009 | 69 | 2009 |
| ClockIt: collecting quantitative data on how beginning software developers really work C Norris, F Barry, JB Fenwick Jr, K Reid, J Rountree ACM SIGCSE Bulletin 40 (3), 37-41, 2008 | 69 | 2008 |
| Methods and apparatus for instruction addressing in indirect VLIW processors EF Barry, GG Pechanek US Patent 6,356,994, 2002 | 68 | 2002 |
| Methods and apparatus for scalable array processor interrupt detection and response EF Barry, PR Marchand, GG Pechanek, LD Larsen US Patent 6,842,811, 2005 | 63 | 2005 |
| Methods and apparatus for providing data transfer control EF Barry, EA Wolff US Patent 6,457,073, 2002 | 59 | 2002 |
| Methods and apparatus for manifold array processing EF Barry, TL Drabenstott, GG Pechanek, NP Pitsianis US Patent 6,769,056, 2004 | 50* | 2004 |
| Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file EF Barry, CW Kurak Jr, GG Pechanek, LD Larsen US Patent 6,397,324, 2002 | 48 | 2002 |
| Methods and apparatus for manarray PE-PE switch control EF Barry, GG Pechanek, TL Drabenstott, EA Wolff, NP Pitsianis, G Morris US Patent 6,167,501, 2000 | 48* | 2000 |
| Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor EF Barry, GG Pechanek, PR Marchand US Patent 6,446,190, 2002 | 43 | 2002 |
| Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor GG Pechanek, JG Revilla, EF Barry US Patent 6,851,041, 2005 | 34 | 2005 |
| Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision GG Pechanek, EF Barry US Patent 6,430,677, 2002 | 34 | 2002 |
| Control processor dynamically loading shadow instruction register associated with memory entry of coprocessor in flexible coupling mode EF Barry US Patent 6,865,663, 2005 | 31 | 2005 |
| Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution TL Drabenstott, GG Pechanek, EF Barry, CW Kurak Jr US Patent 6,954,842, 2005 | 29 | 2005 |
