Andreas Gerstlauer
Andreas Gerstlauer
Associate Professor of Electrical and Computer Engineering, The University of Texas at Austin
Verified email at ece.utexas.edu - Homepage
TitleCited byYear
SpecC: Specification Language and Methodology
DD Gajski, J Zhu, R Doemer, A Gerstlauer, S Zhao
Springer Netherlands, 2000
784*2000
Embedded System Design: Modeling, Synthesis and Verification
DD Gajski, S Abdi, A Gerstlauer, G Schirner
Springer Verlag, 2009
2972009
RTOS Modeling for System Level Design
A Gerstlauer, H Yu, DD Gajski
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2003
2152003
System Design: A Practical Guide with SpecC
A Gerstlauer, R Dömer, J Peng, DD Gajski
Springer Netherlands, 2001
1912001
Electronic system-level synthesis methodologies
A Gerstlauer, C Haubelt, AD Pimentel, TP Stefanov, DD Gajski, J Teich
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2009
1842009
System-on-chip environment: A SpecC-based framework for heterogeneous MPSoC design
R Dömer, A Gerstlauer, J Peng, D Shin, L Cai, H Yu, S Abdi, DD Gajski
EURASIP Journal on Embedded Systems 2008, 5, 2008
1422008
SpecC Language Reference Manual
R Dömer, A Gerstlauer, D Gajski
SpecC Technology Open Consortium, 2002
115*2002
Modeling and synthesis of quality-energy optimal approximate adders
J Miao, K He, A Gerstlauer, M Orshansky
Proceedings of the International Conference on Computer-Aided Design, 728-735, 2012
1122012
Retargetable profiling for rapid, early system-level design space exploration
L Cai, A Gerstlauer, D Gajski
Proceedings of the 41st annual Design Automation Conference, 281-286, 2004
702004
System-level abstraction semantics
A Gerstlauer, DD Gajski
Proceedings of the 15th international symposium on System Synthesis, 231-236, 2002
602002
Approximate logic synthesis under general error magnitude and frequency constraints
J Miao, A Gerstlauer, M Orshansky
Proceedings of the international conference on computer-aided design, 779-786, 2013
532013
Codesign tradeoffs for high-performance, low-power linear algebra architectures
A Pedram, RA Van De Geijn, A Gerstlauer
IEEE Transactions on Computers 61 (12), 1724-1736, 2012
532012
Reliability-aware design to suppress aging
H Amrouch, B Khaleghi, A Gerstlauer, J Henkel
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
502016
RTOS scheduling in transaction level models
H Yu, A Gerstlauer, D Gajski
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware …, 2003
502003
C-based interactive RTL design methodology
D Shin, A Gerstlauer, R Dömer, D Gajski
Center for Embedded Computer Systems, University of California, Irvine, Tech …, 2003
492003
System-on-chip environment (SCE version 2.2. 0 beta): Tutorial
S Abdi, J Peng, H Yu, D Shin, A Gerstlauer, R Dömer, D Gajski
Center for Embedded Computer Systems, University of California, Irvine, Tech …, 2003
49*2003
Design of a GSM Vocoder using SpecC Methodology
A Gerstlauer, S Zhao, D Gajski, A Horak
University of California, Irvine, Technical Report ICSTR-99-11, 1999
471999
System-level communication modeling for network-on-chip synthesis
A Gerstlauer, D Shin, R Dömer, DD Gajski
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
452005
Abstract, multifaceted modeling of embedded processors for system level design
G Schirner, A Gerstlauer, R Domer
Proceedings of the 2007 Asia and South Pacific Design Automation Conference …, 2007
442007
Accurate RTOS modeling and analysis with SystemC
H Zabel, W Müller, A Gerstlauer
Hardware-dependent Software, 233-260, 2009
402009
The system can't perform the operation now. Try again later.
Articles 1–20